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cmos 300 msps quadrature complete dds ad9854 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2007 analog devices, inc. all rights reserved. features 300 mhz internal clock rate fsk, bpsk, psk, chirp, am operation dual integrated 12-bit digital- to-analog converters (dacs) ultrahigh speed comparator, 3 ps rms jitter excellent dynamic performance 80 db sfdr at 100 mhz (1 mhz) a out 4 to 20 programmable reference clock multiplier dual 48-bit programmable frequency registers dual 14-bit programmable phase offset registers 12-bit programmable amplitude modulation and on/off output shaped keying function single-pin fsk and bpsk data interfaces psk capability via input/output interface linear or nonlinear fm chirp functions with single-pin frequency hold function frequency-ramped fsk <25 ps rms total jitter in clock generator mode automatic bidirectional frequency sweeping sin(x)/x correction simplified control interfaces 10 mhz serial 2- or 3-wire spi compatible 100 mhz parallel 8-bit programming 3.3 v single supply multiple power-down functions single-ended or differential input reference clock small, 80-lead lqfp or tqfp with exposed pad applications agile, quadrature lo frequency synthesis programmable clock generators fm chirp source for radar and scanning systems test and measurement equipment commercial and amateur rf exciters functional block diagram digital multipliers system clock dac r set inv sinc filter frequency accumulator acc 1 i/o port buffers comparator programming registers diff/single select reference clock in fsk/bpsk/hold data in bidirectional internal/external i/o update clock read write serial/ parallel select 6-bit address or serial programming lines 8-bit parallel load master reset +v s gnd clock out analog in osk analog out analog out phase-to- amplitude converter programmable amplitude and rate control d q ck 2 int ext system clock ref clk buffer system clock mux delta frequency rate timer system clock delta frequency word frequency tuning word 1 frequency tuning word 2 first 14-bit phase/offset word second 14-bit phase/offset word 12-bit dc control mux system clock phase accumulator acc 2 dds core 12-bit i dac 12-bit q dac or control dac i q 12 mux mux mux mux system clock system clock 48 48 48 14 14 bus 12 12 14 17 17 48 48 48 ad9854 mode select 2 3 demux mux mux 12 inv sinc filter 12 12 12 12 i and q 12-bit am modulation 0 0636-001 4 to 20 ref clk multiplier internal programmable update clock figure 1.
ad9854 rev. e | page 2 of 52 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 general description ......................................................................... 4 specifications..................................................................................... 5 absolute maximum ratings............................................................ 8 thermal resistance ...................................................................... 8 explanation of test levels ........................................................... 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 12 typical applications ....................................................................... 16 theory of operation ...................................................................... 19 modes of operation ................................................................... 19 using the ad9854 .......................................................................... 29 internal and external update clock ........................................ 29 on/off output shaped keying (osk) .................................... 29 i and q dacs.............................................................................. 30 control dac ............................................................................... 30 inverse sinc function ................................................................ 31 refclk multiplier .................................................................... 31 programming the ad9854............................................................ 32 master reset ........................................................................ 32 parallel i/o operation ............................................................... 34 serial port i/o operation.......................................................... 34 general operation of the serial interface ................................... 36 instruction byte .......................................................................... 37 serial interface port pin descriptions ..................................... 37 notes on serial port operation ................................................ 37 msb/lsb transfers......................................................................... 38 control register description.................................................... 38 power dissipation and thermal considerations ....................... 40 thermal impedance................................................................... 40 junction temperature considerations .................................... 40 evaluation of operating conditions........................................ 41 thermally enhanced package mounting guidelines ................ 41 evaluation board ............................................................................ 42 evaluation board instructions.................................................. 42 general operating instructions ............................................... 42 using the provided software .................................................... 44 support ........................................................................................ 44 outline dimensions ....................................................................... 52 ordering guide .......................................................................... 52
ad9854 rev. e | page 3 of 52 revision history 7/07rev. d to rev. e changed ad9854as to ad9854asvz ....................... universal changed AD9854AST to AD9854ASTz......................... universal changes to eneral description .....................................................4 changes to table 1 endnotes...........................................................7 changes to absolute maimum ratings section..........................8 changes to power dissipation section.........................................40 changes to thermally enhanced pacage mounting uidelines section......................................................................41 changes to figure 64 ......................................................................47 changes to outline dimensions ...................................................52 changes to ordering uide...........................................................52 11/06rev. c to rev. d changes to eneral description section .......................................4 changes to endnotes in the power supply parameter .................7 changes to absolute maimum ratings section..........................8 added endnotes to table 2 ..............................................................8 changes to figure 50 ......................................................................29 changes to power dissipation section.........................................39 changes to figure 68 ......................................................................45 updated outline dimensions........................................................51 changes to ordering uide...........................................................51 9/04rev. b to rev. c updated format.................................................................. universal changes to table 1 ............................................................................4 changes to footnote 2 ......................................................................7 changes to eplanation of test levels section .............................8 changes to theory of operation section ....................................17 changes to single tone (mode 000) section...............................17 changes to ramped fsk (mode 010) section............................18 changes to basic fm chirp programming steps section .........23 changes to figure 50 ......................................................................27 changes to evaluation board operating instructions section.40 changes to filtered iout1 and the filtered iout2 section ...41 changes to using the provided software section.......................42 changes to figure 68 ......................................................................45 changes to figure 69 ......................................................................46 updated outline dimensions........................................................50 changes to ordering uide...........................................................50 3/02rev. a to rev. b updated format ................................................................. universal renumbered figures and tables ...................................... universal changes to eneral description section.......................................1 changes to functional bloc diagram ..........................................1 changes to specifications section ..................................................4 changes to absolute maimum ratings section .........................7 changes to pin function descriptions ..........................................8 changes to figure 3 ........................................................................10 deleted two typical performance characteristics raphs........11 changes to inverse sic function section ................................28 changes to differential refclk enable section.......................28 changes to figure 52 ......................................................................30 changes to parallel i/o operation section .................................32 changes to eneral operation of the serial interface section .33 changes to figure 57 ......................................................................34 replaced operating instructions section ....................................40 changes to figure 68 ......................................................................44 changes to figure 69 ......................................................................45 changes to customer evaluation board table............................46
ad9854 rev. e | page 4 of 52 general description the ad9854 digital synthesizer is a highly integrated device that uses advanced dds technology, coupled with two internal high speed, high performance quadrature dacs to form a digitally programmable i and q synthesizer function. when referenced to an accurate clock source, the ad9854 generates highly stable, frequency-phase, amplitude-programmable sine and cosine outputs that can be used as an agile lo in communications, radar, and many other applications. the innovative high speed dds core of the ad9854 provides 48-bit frequency resolution (1 hz tuning resolution with 300 mhz sysclk). maintaining 17 bits ensures excellent sfdr. the circuit architecture of the ad9854 allows the generation of simultaneous quadrature output signals at frequencies up to 150 mhz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. the sine wave output (externally filtered) can be converted to a square wave by the internal comparator for agile clock generator applications. the device provides two 14-bit phase registers and a single pin for bpsk operation. for higher-order psk operation, the i/o interface can be used for phase changes. the 12-bit i and q dacs, coupled with the innovative dds architecture, provide excellent wideband and narrow-band output sfdr. the q dac can also be configured as a user-programmable control dac if the quadrature function is not desired. when configured with the comparator, the 12-bit control dac facilitates static duty cycle control in high speed clock generator applications. two 12-bit digital multipliers permit programmable amplitude modulation, on/off output shaped keying, and precise amplitude control of the quadrature output. chirp functionality is also included to facilitate wide bandwidth frequency sweeping applications. the programmable 4 to 20 refclk multiplier circuit of the ad9854 internally generates the 300 mhz system clock from an external lower frequency reference clock. this saves the user the expense and difficulty of implementing a 300 mhz system clock source. direct 300 mhz clocking is also accommodated with either single- ended or differential inputs. single-pin conventional fsk and the enhanced spectral qualities of ramped fsk are supported. the ad9854 uses advanced 0.35 m cmos technology to provide a high level of functionality on a single 3.3 v supply. the ad9854 is pin-for-pin compatible with the ad9852 single- tone synthesizer. it is specified to operate over the extended industrial temperature range of ?40c to +85c.
ad9854 rev. e | page 5 of 52 specifications v s = 3.3 v 5%, r set = 3.9 k, external reference clock frequency = 30 mhz with refclk multiplier enabled at 10 for ad9854asvz, external reference clock frequency = 20 mhz with refclk multiplier enabled at 10 for AD9854ASTz, unless otherwise noted. table 1. ad9854asvz AD9854ASTz parameter temp test level min typ ma min typ ma unit reference clock input characteristics 1 internal system clock frequency range refclk multiplier enabled full vi 20 300 20 200 mhz refclk multiplier disabled full vi dc 300 dc 200 mhz external reference clock frequency range refclk multiplier enabled full vi 5 75 5 50 mhz refclk multiplier disabled full vi dc 300 dc 200 mhz duty cycle 25c iv 45 50 55 45 50 55 % input capacitance 25c iv 3 3 pf input impedance 25c iv 100 100 k differential mode common-mode voltage range minimum signal amplitude 2 25c iv 400 400 mv p-p common-mode range 25c iv 1.6 1.75 1.9 1.6 1.75 1.9 v v ih (single-ended mode) 25c iv 2.3 2.3 v v il (single-ended mode) 25c iv 1 1 v dac static output characteristics output update speed full i 300 200 msps resolution 25c iv 12 12 bits i and q full-scale output current 25c iv 5 10 20 5 10 20 ma i and q dac dc gain imbalance 3 25c i ?0.5 +0.15 +0.5 ?0.5 +0.15 +0.5 db gain error 25c i ?6 +2.25 ?6 +2.25 % fs output offset 25c i 2 2 a differential nonlinearity 25c i 0.3 1.25 0.3 1.25 lsb integral nonlinearity 25c i 0.6 1.66 0.6 1.66 lsb output impedance 25c iv 100 100 k voltage compliance range 25c i ?0.5 +1.0 ?0.5 +1.0 v dac dynamic output characteristics i and q dac quadrature phase error 25c iv 0.2 1 0.2 1 degrees dac wideband sfdr 1 mhz to 20 mhz a out 25c v 58 58 dbc 20 mhz to 40 mhz a out 25c v 56 56 dbc 40 mhz to 60 mhz a out 25c v 52 52 dbc 60 mhz to 80 mhz a out 25c v 48 48 dbc 80 mhz to 100 mhz a out 25c v 48 48 dbc 100 mhz to 120 mhz a out 25c v 48 48 dbc dac narrow-band sfdr 10 mhz a out (1 mhz) 25c v 83 83 dbc 10 mhz a out (250 khz) 25c v 83 83 dbc 10 mhz a out (50 khz) 25c v 91 91 dbc 41 mhz a out (1 mhz) 25c v 82 82 dbc 41 mhz a out (250 khz) 25c v 84 84 dbc 41 mhz a out (50 khz) 25c v 89 89 dbc 119 mhz a out (1 mhz) 25c v 71 71 dbc 119 mhz a out (250 khz) 25c v 77 77 dbc 119 mhz a out (50 khz) 25c v 83 83 dbc
ad9854 rev. e | page 6 of 52 ad9854asvz AD9854ASTz parameter temp test level min typ max min typ max unit residual phase noise (a out = 5 mhz, external clock = 30 mhz refclk multiplier engaged at 10) 1 khz offset 25c v 140 140 dbc/hz 10 khz offset 25c v 138 138 dbc/hz 100 khz offset 25c v 142 142 dbc/hz (a out = 5 mhz, external clock = 300 mhz, refclk multiplier bypassed) 1 khz offset 25c v 142 142 dbc/hz 10 khz offset 25c v 148 148 dbc/hz 100 khz offset 25c v 152 152 dbc/hz pipeline delays 4 , 5 , 6 dds core (phase accumulator and phase-to-amp converter) 25c iv 33 33 sysclk cycles frequency accumulator 25c iv 26 26 sysclk cycles inverse sinc filter 25c iv 16 16 sysclk cycles digital multiplier 25c iv 9 9 sysclk cycles dac 25c iv 1 1 sysclk cycles i/o update clock (internal mode) 25c iv 2 2 sysclk cycles i/o update clock (external mode) 25c iv 3 3 sysclk cycles master reset duration 25c iv 10 10 sysclk cycles comparator input characteristics input capacitance 25c v 3 3 pf input resistance 25c iv 500 500 k input current 25c i 1 5 1 5 a hysteresis 25c iv 10 20 10 20 mv p-p comparator output characteristics logic 1 voltage, high-z load full vi 3.1 3.1 v logic 0 voltage, high-z load full vi 0.16 0.16 v output power, 50 load, 120 mhz toggle rate 25c i 9 11 9 11 dbm propagation delay 25c iv 3 3 ns output duty cycle error 7 25c i ?10 1 +10 ?10 1 +10 % rise/fall times, 5 pf load 25c v 2 2 ns toggle rate, high-z load 25c iv 300 350 300 350 mhz toggle rate, 50 load 25c iv 375 400 375 400 mhz output cycle-to-cycle jitter 8 iv 4.0 4.0 ps rms comparator narrow-band sfdr 9 10 mhz (1 mhz) 25c v 84 84 dbc 10 mhz (250 mhz) 25c v 84 84 dbc 10 mhz (50 mhz) 25c v 92 92 dbc 41 mhz (1 mhz) 25c v 76 76 dbc 41 mhz (250 mhz) 25c v 82 82 dbc 41 mhz (50 mhz) 25c v 89 89 dbc 119 mhz (1 mhz) 25c v 73 dbc 119 mhz (250 mhz) 25c v 73 dbc 119 mhz (50 mhz) 25c v 83 dbc clock generator output jitter 9 5 mhz a out 25c v 23 23 ps rms 40 mhz a out 25c v 12 12 ps rms 100 mhz a out 25c v 7 7 ps rms
ad9854 rev. e | page 7 of 52 ad9854asvz AD9854ASTz parameter temp test level min typ max min typ max unit parallel i/o timing characteristics t asu (address setup time to wr signal active) full iv 8.0 7.5 8.0 7.5 ns t adhw (address hold time to wr signal inactive) full iv 0 0 ns t dsu (data setup time to wr signal inactive) full iv 3.0 1.6 3.0 1.6 ns t dhd (data hold time to wr signal inactive) full iv 0 0 ns t wrlow ( wr signal minimum low time) full iv 2.5 1.8 2.5 1.8 ns t wrhigh ( wr signal minimum high time) full iv 7 7 ns t wr (minimum wr time) full iv 10.5 10.5 ns t adv (address to data valid time) full v 15 15 15 15 ns t adhr (address hold time to rd signal inactive) full iv 5 5 ns t rdlov ( rd low to output valid) full iv 15 15 ns t rdhoz ( rd high to data three-state) full iv 10 10 ns serial i/o timing characteristics t pre ( cs setup time) full iv 30 30 ns t sclk (period of serial data clock) full iv 100 100 ns t dsu (serial data setup time) full iv 30 30 ns t sclkpwh (serial data clock pulse width high) full iv 40 40 ns t sclkpwl (serial data clock pulse width low) full iv 40 40 ns t dhld (serial data hold time) full iv 0 0 ns t dv (data valid time) full v 30 30 ns cmos logic inputs 10 logic 1 voltage 25c i 2.2 2.2 v logic 0 voltage 25c i 0.8 0.8 v logic 1 current 25c iv 5 12 a logic 0 current 25c iv 5 12 a input capacitance 25c v 3 3 pf power supply 11 , 15 v s current 11, 12 , 15 25c i 1050 1210 755 865 ma v s current 11, 13 , 15 25c i 710 816 515 585 ma v s current 14 25c i 600 685 435 495 ma p diss 11, 12 , 15 25c i 3.475 4.190 2.490 3.000 w p diss 11, 13 , 15 25c i 2.345 2.825 1.700 2.025 w p diss 14 25c i 1.975 2.375 1.435 1.715 w p diss power-down mode 25c i 1 50 1 50 mw 1 the reference clock inputs are configured to accept a 1 v p-p (typical) dc offset square or sine wave centered at one-half the applied v dd or a 3 v ttl-level pulse input. 2 an internal 4 00 mv p-p differential voltage swing equates to 200 mv p-p appl ied to both refclk input pins. 3 the i and q gain imbalance is digitally adjustable to less than 0.01 db. 4 pipeline delays of each individual block are fixed; however, if the first eight msbs of a tuning word are 0s, the delay appear s longer. this is due to insufficient phase accumulation per system clock period to produce enough lsb amplitude to the dac. 5 if a feature such as the inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amoun t. 6 the i/o ud clk transfers data from the i/o port buffers to the programming registers. this transfer is measured in system cloc ks. 7 change in duty cycle from 1 mhz to 100 mhz with 1 v p-p sine wave input and 0.5 v threshold. 8 represents the comparators inherent cycle-to-cycle jitter contribution. the input signal is a 1 v, 40 mhz square wave, and th e measurement device is a wavecrest dts-2075. 9 comparator input originates from the analog output section via the external 7-pole elliptic low-pass filter. single-ended inpu t, 0.5 v p-p. comparator output terminated in 50 . 10 avoid overdriving digital in puts. (refer to the equiva lent circuits in figure 3.) 11 if all device functions are enabled, it is not recommended to simult aneously operate the device at the maximum ambient tempera ture of 85c and at the maximum internal clock frequency. this co nfiguration may result in violating the maximum die junction temperature of 150c. refer to th e power dissipation and thermal considerations section for derating and thermal managem ent information. 12 all functions engaged. 13 all functions except inverse sinc engaged. 14 all functions except inverse sinc and digital multipliers engaged. 15 in most cases, disabling the inverse sinc filt er reduces power consumpt ion by approximately 30%.
ad9854 rev. e | page 8 of 52 absolute maximum ratings table 2. parameter rating maximum junction temperature 150c v s 4 v digital inputs ?0.7 v to +v s digital output current 5 ma storage temperature range ?65c to +150c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c maximum clock frequency (asvz) 300 mhz maximum clock frequency (astz) 200 mhz stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the heat sink of the ad9854asvz 80-lead tqfp package must be soldered to the pcb. table 3. thermal characteristic tqfp lqfp ja (0 m/sec airflow) 1, 2, 3 16.2c/w 38c/w jma (1.0 m/sec airflow) 2, 3, 4, 5 13.7c/w jma (2.5 m/sec airflow) 2, 3, 4, 5 12.8c/w jt 1, 2 0.3c/w jc 6, 7 2.0c/w 1 per jedec jesd51-2 (heat sink soldered to pcb). 2 2s2p jedec test board. 3 values of ja are provided for package comparison and pcb design considerations. 4 per jedec jesd51-6 (heat sink soldered to pcb). 5 airflow increases heat dissipation, effectively reducing ja . furthermore, the more metal that is directly in contact with the package leads from metal traces through holes, ground, and power planes, the more ja is reduced. 6 per mil-std 883, method 1012.1. 7 values of jc are provided for package comparison and pcb design considerations when an extern al heat sink is required. to determine the junction temperature on the application pcb use the following equation: t j t case jt pd where t j is the unction temperature epressed in degrees celsius t case is the case temperature epressed in degrees celsius, as measured by the user at the top center o the package jt cw pd is the power dissipation pd see the power dissipation and thermal considerations section or the method to calculate pd explanation of test levels table 3. test level description i 100% production tested. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi devices are 100% production tested at 25c and guaranteed by design and characterization testing for industrial operating temperature range. esd caution
ad9854 rev. e | page 9 of 52 pin configuration and fu nction descriptions 80 79 78 77 76 71 70 69 68 75 74 73 72 21 22 23 24 25 26 27 28 29 30 31 32 33 1 2 3 4 5 6 7 8 9 10 11 13 12 60 59 58 57 56 55 54 53 52 51 50 49 48 nc = no connect ad9854 top view (not to scale) wr/sclk rd/cs dvdd dvdd dvdd dgnd dgnd dgnd fsk/bpsk/hold osk avdd avdd agnd dvdd dvdd dgnd dgnd dgnd dgnd dvdd dvdd dgnd master reset s/p select refclk refclk d7 d6 d5 d4 d3 d2 d1 d0 dvdd dvdd dgnd dgnd nc avdd agnd nc nc dac r set dacbp avdd agnd iout2 iout2 avdd iout1 iout1 pin 1 indicator 14 15 16 17 18 20 19 47 46 45 44 43 42 41 a5 a4 a3 a2/io reset a1/sdo a0/sdio i/o ud clk agnd agnd agnd avdd vinn vinp agnd 64 63 62 61 67 66 65 34 35 36 37 38 39 40 agnd nc vout avdd avdd agnd agnd agnd agnd avdd diff clk enable nc agnd pll filter 00636-002 figure 2. pin configuration table 4. pin function descriptions pin o. mnemonic description 1 to 8 d7 to d0 8-bit bidirectional parallel programmin g data inputs. used only in parallel programming mode. 9, 10, 23, 24, 25, 73, 74, 79, 80 dvdd connections for the digital circuitry supply volt age. nominally 3.3 v more positive than agnd and dgnd. 11, 12, 26, 27, 28, 72, 75 to 78 dgnd connections for the digital circuitry ground return. same potential as agnd. 13, 35, 57, 58, 63 nc no internal connection. 14 to 16 a5 to a3 parallel address inputs for program registers (part of 6-bit parallel address inputs for program register, a5:a0). used only in parallel programming mode. 17 a2/io reset parallel address input for program registers (part of 6-bit parallel address inputs for program register, a5:a0)/io reset. a2 is used only in parallel programming mode. io reset is used when the serial programming mode is selected, allowing an io reset of the serial communication bus that is unresponsive due to improper programmin g protocol. resetting the serial bus in this manner does not affect previous programming, nor does it invoke the default programming values listed in table 8 . active high. 18 a1/sdo parallel address input for program registers (part of 6-bit parallel address inputs for program register, a5:a0)/unidirectional serial data o utput. a1 is used only in parallel programming mode. sdo is used in 3-wire serial communicati on mode when the serial programming mode is selected. 19 a0/sdio parallel address input for program registers (part of 6-bit parallel address inputs for program register, a5:a0)/bidirectional serial data i/o. a0 is used only in parallel programming mode. sdio is used in 2-wire serial communication mode.
ad9854 rev. e | page 10 of 52 pin no. mnemonic description 20 i/o ud clk bidirectional i/o update clock. direction is selected in control register. if this pin is selected as an input, a rising edge transfers the contents of the i/o port buffers to the programming registers. if i/o ud clk is selected as an output (default), an output pulse (low to high) with a duration of eight system clock cycles indicates that an internal frequency update has occurred. 21 wr /sclk write parallel data to i/o port buffers. shared function with sclk. serial clock signal associated with the serial programming bus. data is registered on the rising edge. this pin is shared with wr when the parallel mode is selected. the mode is dependent on pin 70 (s/p select). 22 rd / cs read parallel data from programming registers. shared function with cs . chip-select signal associated with the serial programming bus. active low. this pin is shared with rd when the parallel mode is selected. 29 fsk/bpsk/hold multifunction pin according to the mode of operation selected in the programming control register. in fsk mode, logic low selects f1 and logic high selects f2. in bpsk mode, logic low selects phase 1 and logic high selects phase 2. in chirp mode, logic high engages the hold function, causing the frequency accumulator to halt at its current location. to resume or commence chirp mode, logic low is asserted. 30 osk output shaped keying. must first be selected in the programming control register to function. a logic high causes the i and q dac outputs to ramp up from zero-sca le to full-scale amplitude at a preprogrammed rate. logic low causes the full-scal e output to ramp down to zero scale at the preprogrammed rate. 31, 32, 37, 38, 44, 50, 54, 60, 65 avdd connections for the analog circuitry supply volt age. nominally 3.3 v more positive than agnd and dgnd. 33, 34, 39, 40, 41, 45, 46, 47, 53, 59, 62, 66, 67 agnd connections for analog circuitry gr ound return. same potential as dgnd. 36 vout noninverted output of the internal high speed comparator. designed to drive 10 dbm to 50 load as well as standard cmos logic levels. 42 vinp voltage input positive. the noninverting input of the internal high speed comparator. 43 vinn voltage input negative. the inverting input of the internal high speed comparator. 48 iout1 unipolar current output of i, or the cosine dac. (refer to figure 3 .) 49 iout1 complementary unipolar current output of i, or the cosine dac. 51 iout2 complementary unipolar current output of q, or the sine dac. 52 iout2 unipolar current output of q, or the sine dac. this dac can be programmed to accept external 12-bit data in lieu of internal sine data, al lowing the ad9854 to emulate the ad9852 control dac function. 55 dacbp common bypass capacitor connection for both i and q dacs. a 0.01 f chip capacitor from this pin to avdd improves harmonic distortion and sfdr slightly. no connect is permissible, but results in a slight degradation in sfdr. 56 dac r set common connection for both i and q dacs. used to set the full-scale output current. r set = 39.9/i out . normal r set range is from 8 k (5 ma) to 2 k (20 ma). 61 pll filter connection for the external zero-compensation network of the refclk multipliers pll loop filter. the zero-compensation network consists of a 1.3 k resistor in series with a 0.01 f capacitor. the other side of the network should be connected to avdd as close as possible to pin 60. for optimum phase noise performance, the re fclk multiplier can be bypassed by setting the bypass pll bit in control register 1e hex. 64 diff clk enable differential refclk enable. a high level of this pin enables the differential clock inputs, refclk and refclk (pin 69 and pin 68, respectively). 68 refclk complementary (180 out of phase) differential cloc k signal. user should tie this pin high or low when single-ended clock mode is selected. same signal levels as refclk. 69 refclk single-ended reference clock input (cmos logic levels required) or one of two differential clock signals. in differential reference clock mode, both inputs can be cmos logic levels or have greater than 400 mv p-p square or sine waves centered about 1.6 v dc. 70 s/p select selects serial programming mode (logic low) or parallel programming mode (logic high). 71 master reset initializes the serial/parallel programming bus to prepare for user programming; sets programming registers to a do-nothing state defined by the default values listed in table 8 . active on logic high. asserting this pin is essential for proper operation upon power-up.
ad9854 rev. e | page 11 of 52 vinp/ vinn avdd i out i outb must terminate outputs for current flow. do not exceed the output voltage compliance rating. comparator out avdd d v dd digital in avoid overdriving digital inputs. forward biasing esd diodes may couple digital noise onto power pins. a. dac outputs b. comparator output c. comparator input d. digital inputs avdd 00636-003 figure 3. equivalent input and output circuits
ad9854 rev. e | page 12 of 52 typical performance characteristics figure 4 to figure 9 indicate the wideband harmonic distortion performance of the ad9854 from 19.1 mhz to 119.1 mhz fundamental output, reference clock = 30 mhz, refclk multiplier = 10. each graph is plotted from 0 mhz to 150 mhz (nyquist). 0 start 0hz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 15mhz/ stop 150mhz 0 0636-004 figure 4. wideband sfdr, 19.1 mhz 0 start 0hz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 15mhz/ stop 150mhz 00636-005 figure 5. wideband sfdr, 39.1 mhz 0 start 0hz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 15mhz/ stop 150mhz 00636-006 figure 6. wideband sfdr, 59.1 mhz 0 start 0hz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 15mhz/ stop 150mhz 00636-007 figure 7. wideband sfdr, 79.1 mhz 0 start 0hz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 15mhz/ stop 150mhz 00636-008 figure 8. wideband sfdr, 99.1 mhz 0 start 0hz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 15mhz/ stop 150mhz 00636-009 figure 9. wideband sfdr, 119.1 mhz
ad9854 rev. e | page 13 of 52 figure 10 to figure 15 show the trade-off in elevated noise floor, increased phase noise (pn), and discrete spurious energy when the internal refclk multiplier circuit is engaged. plots with wide (1 mhz) and narrow (50 khz) spans are shown. compare the noise floor of figure 11 and figure 12 with that of figure 14 and figure 15 . the improvement seen in figure 11 and figure 12 is a direct result of sampling the fundamental at a higher rate. sampling at a higher rate spreads the quantization noise of the dac over a wider ban dwidth, which effectively lowers the noise floor. 0 center 39.1mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 100khz/ span 1mhz 0 0636-010 figure 10. narrow-band sfdr, 39.1 mhz, 1 mhz bw, 300 mhz refclk with refclk multiplier bypassed 0 center 39.1mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 5khz/ span 50khz 00636-011 figure 11. narrow-band sfdr, 39.1 mhz, 50 khz bw, 300 mhz refclk with refclk multiplier bypassed 0 center 39.1mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 5khz/ span 50khz 00636-014 figure 12. narrow-band sfdr, 39.1 mhz, 50 khz bw, 100 mhz refclk with refclk multiplier bypassed 0 center 39.1mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 100khz/ span 1mhz 00636-012 figure 13. narrow-band sfdr, 39.1 mhz, 1 mhz bw, 30 mhz refclk with refclk multiplier = 10 0 center 39.1mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 5khz/ span 50khz 00636-013 figure 14. narrow-band sfdr, 39.1 mhz, 50 khz bw, 30 mhz refclk with refclk multiplier = 10 0 center 39.1mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 5khz/ span 50khz 00636-015 figure 15. narrow-band sfdr, 39.1 mhz, 50 khz bw, 10 mhz refclk with refclk multiplier = 10
ad9854 rev. e | page 14 of 52 figure 16 and figure 17 show the narrow-band performance of the ad9854 when operating with a 200 mhz reference clock with the refclk multiplier bypassed vs. a 20 mhz reference clock and the refclk multiplier enabled at 10. 0 center 39.1mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 5khz/ span 50khz 00636-016 figure 16. narrow-band sfdr, 39.1 mhz, 50 khz bw, 200 mhz refclk with refclk multiplier bypassed 0 center 39.1mhz ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 5khz/ span 50khz 00636-017 figure 17. narrow-band sfdr, 39.1 mhz, 50 khz bw, 20 mhz refclk with refclk multiplier = 10 ? 100 ?110 ?150 ?120 ?130 ?140 ?160 ?170 phase noise (dbc/hz) a out = 80mhz a out =5mhz frequency (hz) 10 1m 100 100k 10k 1k 00636-018 figure 18. residual phase noise, 300 mhz refclk with refclk multiplier bypassed frequency (hz) ? 90 ?100 ?140 ?110 ?120 ?130 ?150 ?160 10 1m 100 100k 10k 1k phase noise (dbc/hz) a out =80mhz a out =5mhz 00636-019 figure 19. residual phase noise, 30 mhz refclk with refclk multiplier = 10 dac current (ma) 55 0 5 10 15 20 25 sfdr (dbc) 54 53 52 51 50 49 48 00636-020 figure 20. sfdr vs. dac current, 59.1 a out , 300 mhz refclk with refclk multiplier bypassed frequency (mhz) 620 0 supply current (ma) 615 610 605 600 595 590 20 40 60 80 100 120 140 00636-021 figure 21. supply current vs. output frequency (variation is minimal, expressed as a percentage, and heavily dependent on tuning word)
ad9854 rev. e | page 15 of 52 rise time 1.04ns 500ps/div 232mv/div 50 ? input jitter [10.6ps rms] ?33ps 0ps +33ps 0 0636-022 figure 22. typical comparator output jitter, 40 mhz a out , 300 mhz rfclk with refclk multiplier bypassed ch1 500mv ? m 500ps ch1 980mv ref1 rise 1.174ns c1 fall 1.286ns 00636-023 figure 23. comparator rise/fall times frequency (mhz) 1200 0 amplitude (mv p-p) 1000 800 600 400 200 0 100 200 300 400 500 minimum comparator input drive v cm =0.5v 00636-024 figure 24. comparator toggle voltage requirement
ad9854 rev. e | page 16 of 52 typical applications lpf refclk rf/if input i baseband cos lpf lpf ad9854 q baseband lpf sin 00636-025 channel select filters figure 25. quadrature downconversion lpf refclk cos lpf ad9854 sin rf output i baseband q baseband 00636-026 figure 26. direct conversion quadrature upconverter i q rx rf in dual 8-/10-bit adc digital demodulator rx baseband digital data out 8 8 i/q mixer and low-pass filter vca adc encode adc clock frequency locked to tx chip/ symbol/pn rate reference clock 48 chip/symbol/pn rate data ad9854 clock generator agc 00636-027 figure 27. chip rate generator in spread spectrum application 50 ? band-p a ss filter 50 ? i out ad9854 fundamental f c ?f o image f clk f c +f o image band-pass filter f c +f o image ad9854 spectrum final output spectrum amplifier 00636-028 figure 28. using an aliased image to generate a high frequency
ad9854 rev. e | page 17 of 52 vco loop filter phase comparator reference clock filter ad9854 dds tuning word ref clk in rf frequency out dac out programmable divide-by-n function (where n = 2 48 /tuning word) 00636-029 figure 29. programmable fractional divide-by-n synthesizer tuning word vco loop filter phase comparator ref clock rf frequency out filter ad9854 dds divide-by-n 00636-030 figure 30. agile high frequency synthesizer phase splitter 0.8 to 2.5ghz ad9854 quadrature dds dds ? lo lo dds +lo 36db typical ssb rejection 50 ? v out ad8346 quadr ature modulator 90 cosine (dc to 70mhz) sine (dc to 70mhz) lo lo 0 0 0636-031 notes 1. flip dds quadrature signals to select alternate sideband. adjust dds sine or cosine signal amplitude for greatest sideband suppression. dds dac outputs must be low-pass filtered prior to use with the ad8346. figure 31. single sideband upconversion reference clock 50? 1:1 transformer (mini-circuits ? t1-1t) filter 50 ? differenti a l transformer-coupled output ad9854 dds i out i out 0 0636-032 figure 32. differential output connectio n for reduction of common-mode signals
ad9854 rev. e | page 18 of 52 clock out = 200mhz lpf sin lpf ad9854 cos reference clock comp a r a tors a out = 100mhz 00636-033 figure 33. clock frequency doubler processor/ controller fpga, etc. r set 8-bit parallel or serial programming data and control signals ad9854 + reference clock 300mhz max direct mode or 15mhz to 75mhz max in the 4 to 20 clock multiplier mode 2k? i dac 1 2 q dac or control dac low-pass filter low-pass filter 00636-034 notes 1. i out = approx 20ma max when r set = 2k ? . 2. switch position 1 provides complementary sinusoidal signals to the comparator to produce a fixed 50% duty cycle from the comparator. 3. switch position 2 provides the same duty cycle using quadrature sinusoidal signals to the comparator or a dc threshold voltage to allow setting of the comparator duty cycle (depends on the configuration of the q dac). cmos logic clock out figure 34. frequency agile clock generator applications for the ad9854
ad9854 rev. e | page 19 of 52 theory of operation the ad9854 quadrature output digital synthesizer is a highly flexible device that addresses a wide range of applications. the device consists of an nco with a 48-bit phase accumulator, a programmable reference clock multiplier, inverse sinc filters, digital multipliers, two 12-bit/300 mhz dacs, a high speed analog comparator, and interface logic. this highly integrated device can be configured to serve as a synthesized lo, an agile clock generator, or an fsk/bpsk modulator. analog devices, inc., provides a technical tutorial about the operational theory of the functional blocks of the device. the tutorial includes a technical description of the signal flow through a dds device and provides basic applications information for a variety of digital synthesis implementations. the document, a technical tutorial on digital signal synthesis, is available from the dds technical library, on the analog devices dds website at www.analog.com/dds . modes of operation the ad9854 has five programmable operational modes. to select a mode, three bits in the control register (parallel address 1f hex) must be programmed, as described in table 5 . table 5. mode selection table mode 2 mode 1 mode 0 result 0 0 0 single tone 0 0 1 fsk 0 1 0 ramped fsk 0 1 1 chirp 1 0 0 bpsk in each mode, some functions may be prohibited. tabl e 6 lists the functions and their availability for each mode. single tone (mode 000) this is the default mode when the master reset pin is asserted. it can also be accessed if the user programs this mode into the control register. the phase accumulator, responsible for generating an output frequency, is presented with a 48-bit value from the frequency tuning word 1 registers that have default values of 0. default values from the remaining applicable registers further define the single-tone output signal qualities. the default values after a master reset configure the device with an output signal of 0 hz and zero phase. at power-up and reset, the output from the i and q dacs is a dc value equal to the midscale output current. this is the default mode amplitude setting of 0. see the on/off output shaped keying (osk) section for more details about the output amplitude control. all or some of the 28 program registers must be programmed to produce a user-defined output signal. figure 35 shows the transition from the default condition (0 hz) to a user-defined output frequency (f1). table 6. functions available for modes mode function single tone fsk ramped fsk chirp bpsk phase adjust 1 phase adjust 2 single-pin fsk/bpsk or hold single-pin shaped keying phase offset or modulation amplitude control or modulation inverse sinc filter frequency tuning word 1 frequency tuning word 2 automatic frequency sweep
ad9854 rev. e | page 20 of 52 000 (single tone) mode f1 tw1 000 (default) 0 f1 0 frequency master reset i/o ud clk 00636-035 figure 35. default state to user-defined output transition as with all analog devices dds devices, the value of the frequency tuning word is determined by ftw = ( desired output frequency 2 n )/ sysclk where: n is the phase accumulator resolution (48 bits in this instance). desired output frequency is expressed in hertz. ftw (frequency tuning word) is a decimal number. after a decimal number has been calculated, it must be rounded to an integer and then converted to binary format, that is, a series of 48 binary-weighted 1s and 0s. the fundamental sine wave dac output frequency range is from dc to one-half sysclk. changes in frequency are phase continuous, meaning that the first sampled phase value of the new frequency is referenced from the time of the last sampled phase value of the previous frequency. the i and q dacs of the ad9854 are always 90 out of phase. the 14-bit phase registers do not independently adjust the phase of each dac output. instead, both dacs are affected equally by a change in phase offset. the single-tone mode allows the user to control the following signal qualities: ? output frequency to 48-bit accuracy ? output amplitude to 12-bit accuracy ? fixed, user-defined amplitude control ? variable, programmable amplitude control ? automatic, programmable, single-pin-controlled on/off output shaped keying ? output phase to 14-bit accuracy these qualities can be changed or modulated via the 8-bit parallel programming port at a 100 mhz parallel byte rate or at a 10 mhz serial rate. incorporating this attribute permits fm, am, pm, fsk, psk, and ask operation in single-tone mode. unramped fsk (mode 001) when the unramped fsk mode is selected, the output frequency of the dds is a function of the values loaded into frequency tuning word register 1 and frequency tuning word register 2 and the logic level of pin 29 (fsk/bpsk/hold). a logic low on pin 29 chooses f1 (frequency tuning word 1, parallel address 4 hex to parallel address 9 hex), and a logic high chooses f2 (frequency tuning word 2, parallel register address a hex to parallel register address f hex). changes in frequency are phase continuous and are internally coincident with the fsk data pin (pin 29); however, there is deterministic pipeline delay between the fsk data signal and the dac output. (refer to the pipeline delays in tabl e 1 .) the unramped fsk mode, shown in figure 36 , represents traditional fsk, radio teletype (rtty), or teletype (tty) transmission of digital data. fsk is a very reliable means of digital communication; however, it makes inefficient use of the bandwidth in the rf spectrum. ramped fsk, shown in figure 37 , is a method of conserving bandwidth. ramped fsk (mode 010) this mode is a method of fsk whereby changes from f1 to f2 are not instantaneous, but are accomplished in a frequency sweep or ramped fashion (the ramped notation implies that the sweep is linear). although linear sweeping, or frequency ramping, is easily and automatically accomplished, it is only one of many schemes. other frequency transition schemes can be implemented by changing the ramp rate and ramp step size on the fly in a piecewise fashion.
ad9854 rev. e | page 21 of 52 f1 f2 0 frequency mode tw1 tw2 fskdata(pin29) 001 (fsk no ramp) f1 f2 000 (default) 0 0 i/o ud clk 00636-036 figure 36. unramped (traditional) fsk mode i/o ud clk f1 f2 0 frequency mode tw1 tw2 010 (ramped fsk) f1 f2 000 (default) 0 0 requires a positive twos complement value ramp rate dfw fskdata(pin29) 00636-037 figure 37. ramped fsk mode (start at f1) f1 f2 0 frequency mode tw1 tw2 fsk data 010 (ramped fsk) f1 f2 000 (default) 0 0 i/o ud clk 00636-038 figure 38. ramped fsk mode (start at f2)
ad9854 rev. e | page 22 of 52 frequency ramping, whether linear or nonlinear, necessitates that many intermediate frequencies between f1 and f2 are output in addition to the primary f1 and f2 frequencies. figure 37 and figure 38 depict the frequency vs. time characteristics of a linear ramped fsk signal. note that in ramped fsk mode, the delta frequency word (dfw) is required to be programmed as a positive twos complement value. another requirement is that the lowest frequency (f1) be programmed in the frequency tuning word 1 register. the purpose of ramped fsk is to provide better bandwidth containment than traditional fsk by replacing the instantaneous frequency changes with more gradual, user-defined frequency changes. the dwell time at f1 and f2 can be equal to or much greater than the time spent at each intermediate frequency. the user controls the dwell time at f1 and f2, the number of inter- mediate frequencies, and the time spent at each frequency. unlike unramped fsk, ramped fsk requires the lowest frequency to be loaded into f1 registers and the highest frequency to be loaded into f2 registers. several registers must be programmed to instruct the dds on the resolution of intermediate frequency steps (48 bits) and the time spent at each step (20 bits). furthermore, the clr acc1 bit in the control register should be toggled (low-high-low) prior to operation to ensure that the frequency accumulator is starting from an all 0s output condition. for piecewise, nonlinear frequency transitions, it is necessary to reprogram the registers while the frequency transition is in progress to affect the desired response. parallel register address 1a hex to parallel register address 1c hex comprise the 20-bit ramp rate clock registers. this is a countdown counter that outputs a single pulse whenever the count reaches 0. the counter is activated when a logic level change occurs on the fsk input, pin 29. this counter is run at the system clock rate, 300 mhz maximum. the time period between each output pulse is given as ( n + 1) system clock period where n is the 20-bit ramp rate clock value programmed by the user. the allowable range of n is from 1 to (2 20 ? 1). the output of this counter clocks the 48-bit frequency accumulator shown in figure 39 . the ramp rate clock determines the amount of time spent at each intermediate frequency between f1 and f2. the counter stops automatically when the destination frequency is achieved. the dwell time spent at f1 and f2 is determined by the duration that the fsk input, pin 29, is held high or low after the destination frequency has been reached. frequency tuning word 2 frequency tuning word 1 20-bit ramp rate clock 48-bit delta frequency word (twos complement) frequency accumulator phase accumulator instantaneous phase out adder fsk(pin29) system clock 00636-039 figure 39. block diagram of ramped fsk function parallel register address 10 hex to parallel register address 15 hex comprise the 48-bit, twos complement, delta frequency word registers. this 48-bit word is accumulated (added to the accumulators output) every time it receives a clock pulse from the ramp rate counter. the output of this accumulator is added to or subtracted from the f1 or f2 frequency word, which is then fed into the input of the 48-bit phase accumulator that forms the numerical phase steps for the sine and cosine wave outputs. in this fashion, the output frequency is ramped up and down in frequency according to the logic state of pin 29. this ramping rate is a function of the 20-bit ramp rate clock. when the destination frequency is achieved, the ramp rate clock is stopped, halting the frequency accumulation process. generally speaking, the delta frequency word is a much smaller value compared with the value of the f1 or f2 tuning word. for example, if f1 and f2 are 1 khz apart at 13 mhz, the delta frequency word might be only 25 hz.
ad9854 rev. e | page 23 of 52 f1 f2 0 frequency mode tw1 tw2 fsk data triangle bit 010 (ramped fsk) f1 f2 i/o ud clk 0 0636-040 figure 40. effect of triangle bit in ramped fsk mode f1 f2 0 frequency mode tw1 tw2 fsk data f1 f2 000 (default) 0 0 010 (ramped fsk) i/o ud clk 00636-041 figure 41. effect of premature ramped fsk data figure 41 shows that premature toggling causes the ramp to immediately reverse itself and proceed at the same rate and resolution until the original frequency is reached. the control register contains a triangle bit at parallel register address 1f hex. setting this bit high in mode 010 causes an automatic ramp-up and ramp-down between f1 and f2 to occur without toggling pin 29, as shown in figure 40 . the logic state of pin 29 has no effect once the triangle bit is set high. this function uses the ramp rate clock time period and the step size of the delta frequency word to form a continuously sweeping linear ramp from f1 to f2 and back to f1 with equal dwell times at every frequency. use this function to automatically sweep between any two frequencies from dc to nyquist. in the ramped fsk mode with the triangle bit set high, an automatic frequency sweep begins at either f1 or f2, according to the logic level on pin 29 (fsk input pin) when the triangle bits rising edge occurs ( figure 42 ). if the fsk data bit is high instead of low, f2, rather than f1, is chosen as the start frequency. additional flexibility in the ramped fsk mode is provided by the ad9854s ability to respond to changes in the 48-bit delta frequency word and/or the 20-bit ramp rate counter at any time during the ramping from f1 to f2 or vice versa. to create these nonlinear frequency changes, it is necessary to combine several linear ramps with different slopes in a piecewise fashion. this is done by programming and executing a linear ramp at a rate or slope and then altering the slope (by changing the ramp rate clock or delta frequency word, or both). changes in slope can be made as often as needed before the destination frequency has been reached to form the desired nonlinear frequency sweep response. these piecewise changes can be precisely timed using
ad9854 rev. e | page 24 of 52 the 32-bit internal update clock (see the internal and external update clock section). nonlinear ramped fsk has the appearance of the chirp function shown in figure 43 . the difference between a ramped fsk function and a chirp function is that fsk is limited to operation between f1 and f2, whereas chirp operation has no f2 limit frequency. two additional control bits (clr acc1 and clr acc2) are available in the ramped fsk mode that allow more options. if clr acc1 (register address 1f hex) is set high, it clears the 48-bit frequency accumulator (acc1) output with a retriggerable one-shot pulse of one system clock duration. if the clr acc1 bit is left high, a one-shot pulse is delivered on the rising edge of every update clock. the effect is to interrupt the current ramp, reset the frequency to the start point (f1 or f2), and then continue to ramp up (or down) at the previous rate. this occurs even when a static f1 or f2 destination frequency has been achieved. alternatively, the clr acc2 control bit (register address 1f hex) is available to clear both the frequency accumulator (acc1) and the phase accumulator (acc2). when this bit is set high, the output of the phase accumulator results in 0 hz output from the dds. as long as this bit is set high, the frequency and phase accumulators are cleared, resulting in 0 hz output. to return to previous dds operation, clr acc2 must be set to logic low. chirp (mode 011) this mode is also known as pulsed fm. most chirp systems use a linear fm sweep pattern, but the ad9854 can also support nonlinear patterns. in radar applications, use of chirp or pulsed fm allows operators to significantly reduce the output power needed to achieve the result that a single-frequency radar system would produce. figure 43 shows a very low resolution nonlinear chirp, demonstrating the different slopes that are created by varying the time steps (ramp rate) and frequency steps (delta frequency word). f2 f1 0 frequency mode tw1 tw2 fsk data t riangle bit 000 (default) 0 0 010 (ramped fsk) f1 f2 00636-042 figure 42. automatic linear ramping using the triangle bit f1 0 frequency 010 (ramped fsk) f1 000 (default) 0 mode tw1 dfw r a mp rate i/o ud clk 00636-043 figure 43. example of a nonlinear chirp
ad9854 rev. e | page 25 of 52 the ad9854 permits precise, internally generated linear, or externally programmed nonlinear, pulsed or continuous fm over the complete frequency range, duration, frequency resolution, and sweep direction(s). all of these are user programmable. figure 44 shows a block diagram of the fm chirp components. 20-bit ramp rate clock 48-bit delta frequency word (twos complement) frequency accumulator phase accumulator out adder system clock clr acc2 clr acc1 frequency tuning word 1 hold 00636-044 figure 44. fm chirp components basic fm chirp programming steps 1. program a start frequency into frequency tuning word 1 (ftw1) at parallel register address 4 hex to parallel register address 9 hex. 2. program the frequency step resolution into the 48-bit, twos complement delta frequency word (parallel register address 10 hex to parallel register address 15 hex). 3. program the rate of change (time at each frequency) into the 20-bit ramp rate clock (parallel register address 1a hex to parallel register address 1c hex). when programming is complete, an i/o update pulse at pin 20 engages the program commands. the necessity for a twos complement delta frequency word is to define the direction in which the fm chirp moves. if the 48-bit delta frequency word is negative (msb is high), the incremental frequency changes are in a negative direction from ftw1. if the 48-bit word is positive (msb is low), the incremental frequency changes are in a positive direction from ftw1. it is important to note that ftw1 is only a starting point for fm chirp. there is no built-in restraint requiring a return to ftw1. once the fm chirp begins, it is free to move (under program control) within the nyquist bandwidth (dc to one-half the system clock). however, instant return to ftw1 can be easily achieved. two control bits (clr acc1 and clr acc2) are available in the fm chirp mode that allow the return to the beginning frequency, ftw1, or to 0 hz. when the clr acc1 bit (register address 1f hex) is set high, the 48-bit frequency accumulator (acc1) output is cleared with a retriggerable one-shot pulse of one system clock duration. the 48-bit delta frequency word input to the accumulator is unaffected by the clr acc1 bit. if the clr acc1 bit is held high, a one-shot pulse is delivered to the frequency accumulator (acc1) on every rising edge of the i/o update clock. the effect is to interrupt the current chirp, reset the frequency to that programmed into ftw1, and continue the chirp at the previously programmed rate and direction. clearing the output of the frequency accumulator in the chirp mode is illustrated in figure 45 . shown in the diagram is the i/o update clock, which is either user supplied or internally generated. alternatively, the clr acc2 control bit (register address 1f hex) is available to clear both the frequency accumulator (acc1) and the phase accumulator (acc2). when this bit is set high, the output of the phase accumulator results in 0 hz output from the dds. as long as this bit is set high, the frequency and phase accumulators are cleared, resulting in 0 hz output. to return to the previous dds operation, clr acc2 must be set to logic low. this bit is useful in generating pulsed fm. figure 46 illustrates the effect of the clr acc2 bit on the dds output frequency. note that reprogramming the registers while the clr acc2 bit is high allows a new ftw1 frequency and slope to be loaded. another function that is available only in chirp mode is the hold pin (pin 29). this function stops the clock signal to the ramp rate counter, halting any further clocking pulses to the frequency accumulator, acc1. the effect is to halt the chirp at the frequency existing just before the hold pin is pulled high. when pin 29 is returned low, the clock and chirp resumes. during a hold condition, the user can change the programming registers; however, the ramp rate counter must resume operation at its previous rate until a count of 0 is obtained before a new ramp rate count can be loaded. figure 47 shows the effect of the hold function on the dds output frequency.
ad9854 rev. e | page 26 of 52 i/o ud clk f1 0 frequency mode ftw1 dfw f1 000 (default) 0 r a mp rate ramp rate 011 (chirp) delta frequency word clr acc1 00636-045 figure 45. effect of clr acc1 in fm chirp mode clr acc2 f1 0 frequency mode tw1 dpw 000 (default) 0 r a mp rate 011 (chirp) i/o ud clk 00636-046 figure 46. effect of cl r acc2 in chirp mode
ad9854 rev. e | page 27 of 52 hold f1 0 frequency mode tw1 dfw 000 (default) 0 ramp rate 011 (chirp) f1 delta frequency word ramp rate i/o ud clk 00636-047 figure 47. example of hold function bpsk data 360 0 phase mode ftw1 phase adjust 1 000 (default) 0 phase adjust 2 100 (bpsk) f1 270 90 i/o ud clk 00636-048 figure 48. bpsk mode the 32-bit automatic i/o update counter can be used to construct complex chirp or ramped fsk sequences. because this internal counter is sync hronized with the ad9854 system clock, precisely timed program changes are possible. for such changes, the user need only reprogram the desired registers before the automatic i/o update clock is generated. in chirp mode, the destination frequency is not directly specified. if the user fails to control the chirp, the dds automatically confines itself to the frequency range between dc and nyquist. unless terminated by the user, the chirp continues until power is removed. when the chirp destination frequency is reached, the user can choose any of the following actions: ? stop at the destination frequency by using the hold pin or by loading all 0s into the delta frequency word registers of the frequency accumulator (acc1). ? use the hold pin function to stop the chirp, and then ramp down the output amplitude by using the digital multiplier stages and the output shaped keying pin (pin 30), or by using the program register control (address 21 to address 24 hex). ? abruptly end the transmission with the clr acc2 bit. ? continue chirp by reversing direction and returning to the previous or another destination frequency in a linear or user-directed manner. if this involves reducing the frequency, a negative 48-bit delta frequency word (the msb is set to 1) must be loaded into register 10 hex to register 15 hex. any decreasing frequency step of the delta frequency word requires the msb to be set to logic high.
ad9854 rev. e | page 28 of 52 h, it s phase put carrier. 2. o phase ster 2. 4. activate the i/o update clock when ready. ct 1 using the serial or high speed parallel programming bus. ? continue chirp by immediately returning to the beginning frequency (f1) in a sawtooth fashion, and then repeating the previous chirp process using the clr acc1 control bit. an automatic, repeating chirp can be set up by using the 32-bit update clock to issue the clr acc1 command at precise time intervals. adjusting the timing intervals or changing the delta frequency word changes the chirp range. it is incumbent upon the user to balance the chirp duration and frequency resolution to achieve the proper frequency range. bpsk (mode 100) binary, biphase, or bipolar phase shift keying is a means to rapidly select between two preprogrammed 14-bit output phase offsets that equally affect both the i and q outputs of the ad9854. the logic state of pin 29, the bpsk pin, controls the selection of phase adjust register 1 or phase adjust register 2. when low, pin 29 selects phase adjust register 1; when hig selects phase adjust register 2. figure 48 illustrate changes made to four cycles of an out basic bpsk programming steps 1. program a carrier frequency into frequency tuning word 1. program the appropriate 14-bit phase words int adjust register 1 and phase adjust regi 3. attach the bpsk data source to pin 29. note that for higher-order psk modulation, the user can sele the single-tone mode and program phase adjust register
ad9854 rev. e | page 29 of 52 using the ad9854 internal and external update clock this update clock function is comprised of a bidirectional i/o pin (pin 20) and a programmable 32-bit down-counter. to program changes that are to be transferred from the i/o buffer registers to the active core of the dds, a clock signal (low-to- high edge) must be externally supplied to pin 20 or internally generated by the 32-bit update clock. when the user provides an external update clock, it is internally synchronized with the system clock to prevent a partial transfer of program register information due to a violation of data setup or hold time. this mode allows the user to completely control when updated program information becomes effective. the default mode for the update clock is internal (the internal update clock control register bit is logic high). to switch to external update clock mode, the internal update clock control register bit must be set to logic low. the internal update mode generates automatic, periodic update pulses at intervals set by the user. an internally generated update clock can be established by programming the 32-bit update clock registers (address 16 hex to address 19 hex) and setting the internal update clock control register bit (address 1f hex) to logic high. the update clock down-counter function operates at half the rate of the system clock (150 mhz maximum) and counts down from a 32-bit binary value (programmed by the user). when the count reaches 0, an automatic i/o update of the dds output or functions is generated. the update clock is internally and externally routed to pin 20 to allow users to synchronize the programming of update information with the update clock rate. the time between update pulses is given as ( n + 1)( system clock period 2) where n is the 32-bit value programmed by the user, and the allowable range of n is from 1 to (2 32 ? 1). the internally generated update pulse that is output from pin 20 has a fixed high time of eight system clock cycles. programming the update clock register to a value less than five causes the i/o ud clk pin to remain high. although the update clock can function in this state, it cannot be used to indicate when data is transferring. this is an effect of the minimum high pulse time when i/o ud clk functions as an output. on/off output shaped keying (osk) the on/off osk feature allows the user to control the amplitude vs. time slope of the i and q dac output signals. this function is used in burst transmissions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. users must first enable the digital multipliers by setting the osk en bit (control register address 20 hex) to logic high in the control register. otherwise, if the osk en bit is set low, the digital multipliers responsible for amplitude control are bypassed and the i and q dac outputs are set to full-scale amplitude. in addition to setting the osk en bit, a second control bit, osk int (also at address 20 hex), must be set to logic high. logic high selects the linear internal control of the output ramp-up or ramp- down function. a logic low in the osk int bit switches control of the digital multipliers to user-programmable 12-bit registers, allowing users to dynamically shape the amplitude transition in practically any fashion. these 12-bit registers, labeled output shape key i and output shape key q, are located at address 21 hex through address 24 hex, as listed in table 8 . the maximum output amplitude is a function of the r set resistor and is not programmable when osk int is enabled. a brupt on / off keying shaped on/off keying zero scale zero scale full scale full scale 00636-049 figure 49. on/off output shaped keying the transition time from zero scale to full scale must also be programmed. the transition time is a function of two fixed elements and one variable. the variable element is the program- mable 8-bit ramp rate counter. this is a down-counter that is clocked at the system clock rate (300 mhz maximum) and that generates one pulse whenever the counter reaches 0. this pulse is routed to a 12-bit counter that increments with each pulse received. the outputs of the 12-bit counter are connected to the 12-bit digital multiplier. when the digital multiplier has a value of all 0s at its inputs, the input signal is multiplied by 0, producing zero scale. when the multiplier has a value of all 1s, the input signal is multiplied by a value of 4095 or 4096, producing nearly full scale. there are 4094 remaining fractional multiplier values that produce output amplitudes scaled according to their binary values.
ad9854 rev. e | page 30 of 52 12-bit digital multiplier 12 12 (byp a ss multiplier) osk en = 0 osk en = 1 osk en = 0 osk en = 1 12 12 digital signal in user-programmable 12-bit q channel multiplier output shaped keying q multiplier register 12 osk int = 0 osk int = 0 1 8-bit ramp rate counter system clock on/off output shaped keying pin sine dac 12-bit up/down counter dds digital output 00636-050 figure 50. block diagram of q dac pathway of the digital multiplier section responsible for the output shaped keying function the two fixed elements of the transition time are the period of the system clock (which drives the ramp rate counter) and the number of amplitude steps (4096). for example, if the system clock of the ad9854 is 100 mhz (10 ns period) and the ramp rate counter is programmed for a minimum count of 3, the transition takes two system clock periods (one rising edge loads the countdown value, and the next edge decrements the counter from 3 to 2). if the countdown value is less than 3, the ramp rate counter stalls and therefore produces a constant scaling value to the digital multipliers. this stall condition may have an application for the user. the relationship of the 8-bit countdown value to the time between output pulses is given as ( n + 1) system clock period where n is the 8-bit countdown value. it takes 4096 of these pulses to advance the 12-bit up-counter from zero scale to full scale. therefore, the minimum output shaped keying ramp time for a 100 mhz system clock is 4096 4 10 ns 164 s the maximum ramp time is 4096 256 10 ns 10.5 ms finally, changing the logic state of pin 30, output shaped keying automatically performs the programmed output envelope functions when osk int is high. a logic high on pin 30 causes the outputs to linearly ramp up to full-scale amplitude and to hold until the logic level is changed to low, causing the outputs to ramp down to zero scale. i and q dacs the sine and cosine outputs of the dds drive the q and i dacs, respectively (300 msps maximum). the maximum amplitudes of these output are set by the dac r set resistor at pin 56. these are current-output dacs with a full-scale maximum output of 20 ma; however, a nominal 10 ma output current provides the best spurious-free dynamic range (sfdr) performance. the value of r set is 39.93/i out , where i out is expressed in amps. dac output compliance specifications limit the maximum voltage developed at the outputs to ?0.5 v to +1 v. voltages developed beyond this limitation cause excessive dac distortion and possibly permanent damage. the user must choose a proper load impedance to limit the output voltage swing to the compliance limits. both dac outputs should be terminated equally for best sfdr, especially at higher output frequencies, where harmonic distortion errors are more prominent. both dacs are preceded by inverse sin(x)/x filters (also called inverse sinc filters) that precompensate for dac output amplitude variations over frequency to achieve flat amplitude response from dc to nyquist. both dacs can be powered down when not needed by setting the dac pd bit high (address 1d hex of the control register). i dac outputs are designated as iout1 and iout1 , pin 48 and pin 49, respectively. q dac outputs are designated as iout2 and iout2 , pin 52 and pin 51, respectively. control dac the 12-bit q dac can be reconfigured to perform as a control or auxiliary dac. the control dac output can provide dc control levels to external circuitry, generate ac signals, or enable duty cycle control of the on-board comparator. when the src q dac bit in the control register (parallel address 1f hex) is set high, the q dac inputs are switched from internal 12-bit q data source (default setting) to external 12-bit, twos complement data supplied by the user. data is channeled through the serial or parallel interface to the 12-bit q dac register (address 26 hex and address 27 hex) at a maximum data rate of 100 mhz. this dac is clocked at the system clock, 300 msps (maximum), and has the same maximum output current capability as that of the i dac. the single r set resistor on the ad9854 sets the full-scale output current for both dacs. when not needed, the control dac can be separately powered down to conserve power by setting the q dac power-down bit high (address 1d hex). control dac outputs are designated as iout2 and iout2 , pin 52 and pin 51, respectively.
ad9854 rev. e | page 31 of 52 inverse sinc function the inverse sinc function precompensates input data to both dacs for the sin(x)/x roll-off characteristic inherent in the dacs output spectrum. this allows wide bandwidth signals (such as qpsk) to be output from the dacs without appreciable amplitude variations as a function of frequency. the inverse sinc function can be bypassed to reduce power consumption significantly, especially at higher clock speeds. when the q dac is configured as a control dac, the inverse sinc function does not apply to the q path. inverse sinc is engaged by default and is bypassed by bringing the bypass inverse sinc bit high in control register 20 hex, as noted in table 8 . frequency normalized to sample rate 4.0 00.1 ?0.5 0 magnitude (db) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 0.2 0.3 0.4 0.5 system isf sinc 00636-051 figure 51. inverse sinc filter response refclk multiplier the refclk multiplier is a programmable pll-based reference clock multiplier that allows the user to select an integer clock multiplying value over the range of 4 to 20. with this function, users can input as little as 15 mhz at the refclk input to produce a 300 mhz internal system clock. five bits in control register 1e hex set the multiplier value, as detailed in tabl e 7 . the refclk multiplier function can be bypassed to allow direct clocking of the ad9854 from an external clock source. the system clock for the ad9854 is either the output of the refclk multiplier (if it is engaged) or the refclk inputs. refclk can be either a single-ended or differential input by setting pin 64, diff clk enable, low or high, respectively. pll range bit the pll range bit selects the frequency range of the refclk multiplier pll. for operation from 200 mhz to 300 mhz (internal system clock rate), the pll range bit should be set to logic 1. for operation below 200 mhz, the pll range bit should be set to logic 0. the pll range bit adjusts the pll loop parameters for best phase noise performance within each range. pll filter the pll filter pin (pin 61) provides the connection for the external zero-compensation network of the pll loop filter. the zero-compensation network consists of a 1.3 k resistor in series with a 0.01 f capacitor. the other side of the network should be connected as close as possible to pin 60, avdd. for optimum phase noise performance, the clock multiplier can be bypassed by setting the bypass pll bit in control register address 1e hex. differential refclk enable a high level on the diff clk enable pin enables the differ- ential clock inputs, refclk and refclk (pin 69 and pin 68, respectively). the minimum differential signal amplitude required is 400 mv p-p at the refclk input pins. the center point or common-mode range of the differential signal can range from 1.6 v to 1.9 v. when pin 64 (diff clk enable) is tied low, refclk (pin 69) is the only active clock input. this is referred to as single-ended mode. in this mode, pin 68 ( refclk ) should be tied low or high. high speed comparator the comparator is optimized for high speed and has a toggle rate greater than 300 mhz, low jitter, sensitive input, and built-in hysteresis. it also has an output level of 1 v p-p minimum into 50 or cmos logic levels into high impedance loads. the comparator can be powered down separately to conserve power. this com- parator is used in clock-generator applications to square up the filtered sine wave generated by the dds. power-down the programming registers allow several individual stages to be powered down to reduce power consumption while maintaining the functionality of the desired stages. these stages are identified in table 8 , address 1d hex. power-down is achieved by setting the specified bits to logic high. a logic low indicates that the stages are powered up. furthermore, and perhaps most significantly, the inverse sinc filters and the digital multiplier stages can be bypassed to achieve significant power reduction by programming the control registers in address 20 hex. again, logic high causes the stage to be bypassed. of particular importance is the inverse sinc filter; this stage consumes a significant amount of power. a full power-down occurs when all four pd bits in control register 1d hex are set to logic high. this reduces power consumption to approximately 10 mw (3 ma).
ad9854 rev. e | page 32 of 52 programming the ad9854 the ad9854 register layout table ( table 8 ) contains information for programming the chip for the desired functionality. although many applications require very little programming to configure the ad9854, some use all 12 accessible register banks. the ad9854 supports an 8-bit parallel i/o operation or an spi?- compatible serial i/o operation. all accessible registers can be written and read back in either i/o operating mode. s/p select (pin 70) is used to configure the i/o mode. systems that use the parallel i/o mode must connect the s/p select pin to v dd . systems that operate in the serial i/o mode must tie the s/p select pin to gnd. regardless of the mode, the i/o port data is written to a buffer memory and only affects operation of the part after the contents of the buffer memory are transferred to the register banks. this transfer of information occurs synchronously to the system clock in one of two ways: ? internally, at a rate programmable by the user. ? externally, by the user. i/o operations can occur in the absence of refclk, but the data cannot be moved from the buffer memory to the register bank without refclk. (see the internal and external update clock section for more details.) master reset the master reset pin must be held at logic high active for a minimum of 10 system clock cycles. this initializes the communications bus and loads the default values listed in the table 8 section. table 7. refclk multiplier control register values reference multiplier multiplier value bit 4 bit 3 bit 2 bit 1 bit 0 4 0 0 1 0 0 5 0 0 1 0 1 6 0 0 1 1 0 7 0 0 1 1 1 8 0 1 0 0 0 9 0 1 0 0 1 10 0 1 0 1 0 11 0 1 0 1 1 12 0 1 1 0 0 13 0 1 1 0 1 14 0 1 1 1 0 15 0 1 1 1 1 16 1 0 0 0 0 17 1 0 0 0 1 18 1 0 0 1 0 19 1 0 0 1 1 20 1 0 1 0 0
ad9854 rev. e | page 33 of 52 table 8. register layout 1 ad9854 register layout parallel address (hex) serial address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value (hex) 00 0 phase adjust register 1 <13:8> (bits 15, 14, dont care) phase 1 00 01 phase adjust register 1 <7:0> 00 02 1 phase adjust register 2 <13:8> (bits 15, 14, dont care) phase 2 00 03 phase adjust register 2 <7:0> 00 04 2 frequency tuning word 1 <47:40> freq 1 00 05 frequency tuning word 1 <39:32> 00 06 frequency tuning word 1 <31:24> 00 07 frequency tuning word 1 <23:16> 00 08 frequency tuning word 1 <15:8> 00 09 frequency tuning word 1 <7:0> 00 0a 3 frequency tuning word 2 <47:40> 0b frequency tuning word 2 <39:32> 00 0c frequency tuning word 2 <31:24> 00 0d frequency tuning word 2 <23:16> 00 0e frequency tuning word 2 <15:8> 00 0f frequency tuning word 2 <7:0> 00 10 4 delta frequency word <47:40> 00 11 delta frequency word <39:32> 00 12 delta frequency word <31:24> 00 13 delta frequency word <23:16> 00 14 delta frequency word <15:8> 00 15 delta frequency word <7:0> 00 16 5 update clock <31:24> 00 17 update clock <23:16> 00 18 update clock <15:8> 00 19 update clock <7:0> 40 1a 6 ramp rate clock <19:16> (bits 23, 22, 21, 20, dont care) 00 1b ramp rate clock <15:8> 00 1c ramp rate clock <7:0> 00 1d 7 dont care cr [31] dont care dont care comp pd reserved, always low qdac pd dac pd dig pd 10 1e dont care pll range bypass pll ref mult 4 ref mult 3 ref mult 2 ref mult 1 ref mult 0 64 1f clr acc 1 clr acc 2 triangle src qdac mode 2 mode 1 mode 0 internal/external update clock 01 20 dont care bypass inv sinc osk en osk int dont care dont care lsb first sdo active cr [0] 20 21 8 output shaped keying i multiplier <11:8> (bits 15, 14, 13, 12 dont care) 00 22 output shaped keying i multiplier <7:0> 00 23 9 output shaped keying q multiplier <11:8> (bits 15, 14, 13, 12 dont care) 00 24 output shaped keying q multiplier <7:0> 00 25 a output shaped keying ramp rate <7:0> 80 26 b qdac <11:8> (bits 15, 14, 13, 12 dont care) 00 27 qdac <7:0> (data is required to be in twos complement format) 1 the shaded sections comprise the control register.
ad9854 rev. e | page 34 of 52 parallel i/o operation with the s/p select pin tied high, the parallel i/o mode is active. the i/o port is compatible with industry-standard dsps and microcontrollers. six address bits, eight bidirectional data bits, and separate write/read control inputs comprise the i/o port pins. parallel i/o operation allows write access to each byte of any register in a single i/o operation of up to one per 10.5 ns. readback capability for each register is included to ease designing with the ad9854. (reads are not guaranteed at 100 mhz because they are intended for software debugging only.) parallel i/o operation timing diagrams are shown in figure 52 and figure 53 . serial port i/o operation with the s/p select pin tied low, the serial i/o mode is active. the serial port is a flexible, synchronous, serial communication port, allowing easy interface to many industry-standard micro- controllers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola? 6905/11 spi and intel? 8051 ssr protocols. the interface allows read/write access to all 12 registers that configure the ad9854 and can be configured as a single-pin i/o (sdio) or two unidirectional pins for input and output (sdio/sdo). data transfers are supported in msb-or the lsb-first format for up to 10 mhz. when configured for serial i/o operation, most ad9854 parallel port pins are inactive; only some pins are used for the serial i/o operation. table 9 describes pin requirements for serial i/o operation. note that when operating the device in serial i/o mode, it is best to use the external i/o update clock mode to avoid an update occurring during a serial communication cycle. such an occurrence may cause incorrect programming due to a partial data transfer. to exit the default internal update mode, program the device for external update operation at power-up before starting the refclk signal but after a master reset. starting the refclk causes this information to transfer to the register bank, forcing the device to switch to external update mode. table 9. serial i/o pin requirements pin number mnemonic serial i/o description 1 to 8 d [7:0] the parallel data pins are not active; tie to vdd or gnd. 14 to 16 a [5:3] the a5, a4, and a3 parallel address pi ns are not active; tie these pins to vdd or gnd. 17 a2/io reset io reset. 18 a1/sdo sdo. 19 a0/sdio sdio. 20 i/o ud clk update clock. same function ality for serial mode as parallel mode. 21 wr /sclk sclk. 22 rd / cs cs chip select.
ad9854 rev. e | page 35 of 52 a<5:0> d<7:0> a1 d1 a2 d2 a3 d3 t rdhoz t rdlov t ahd t adv specification value description t adv t ahd t rdlov t rdhoz 15ns 5ns 15ns 10ns address to data valid time (maximum) address hold time to rd signal inactive (minimum) rd low to output valid (maximum) rd high to data three-state (maximum) rd 00636-052 figure 52. parallel port read timing diagram d<7:0> d1 d2 d3 specification value description t asu t dsu t adh t dhd 8.0ns 3.0ns address setup time to wr signal active data setup time to wr signal active 0ns 0ns address hold time to wr signal inactive data hold time to wr signal inactive t wrlow t wrhigh t wr 2.5ns wr signal minimum low time 7ns 10.5ns wr signal minimum high time minimum write time a <5:0> a1 a2 a3 t asu t ahd t wrhigh t wrlow t dhd t dsu t wr wr 0 0636-053 figure 53. parallel port write timing diagram
ad9854 rev. e | page 36 of 52 general operation of the serial interface there are two phases of a serial communication cycle with the ad9854. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9854 coincident with the first eight sclk rising edges. the instruction byte provides the ad9854 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is a read or write and the register address to be acted upon. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9854. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9854 and the system controller. the number of data bytes transferred in phase 2 of the communication cycle is a function of the register address. ( tabl e 10 describes how many bytes must be transferred.) the ad9854 internal serial i/o controller expects every byte of the register being accessed to be transferred. therefore, the user should write between i/o update clocks. at the completion of a communication cycle, the ad9854 serial port controller expects the subsequent eight rising sclk edges to be the instruction byte of the next communication cycle. in addition, an active high input on the io reset pin immediately terminates the current communication cycle. after io reset returns low, the ad9854 serial port controller requires the subsequent eight rising sclk edges to be the instruction byte of the next communication cycle. all data input to the ad9854 is registered on the rising edge of sclk, and all data is driven out of the ad9854 on the falling edge of sclk. figure 54 and figure 55 show the general operation of the ad9854 serial port. table 10. register address vs. data bytes transferred serial register address register ame umber of bytes transferred 0 phase offset tuning word register 1 2 1 phase offset tuning word register 2 2 2 frequency tuning word 1 6 3 frequency tuning word 2 6 4 delta frequency register 6 5 update clock rate register 4 6 ramp rate clock register 3 7 control register 4 8 i path digital multiplier register 2 9 q path digital multiplier register 2 a shaped on/off keying ramp rate register 1 b q dac register 2 instruction cycle data transfer instruction byte data byte 1 data byte 2 data byte 3 sdio cs 00636-054 figure 54. using sdio as a read/write transfer instruction cycle data transfer instruction byte s dio data transfer data byte 1 data byte 2 data byte 3 sdo cs 00636-055 figure 55. using sdio as an input and sdo as an output
ad9854 rev. e | page 37 of 52 instruction byte the instruction byte contains the following information: msb l sb d7 d6 d5 d4 d3 d2 d1 d0 r/ w x x x a3 a2 a1 a0 r/ w bit 7 determines whether a read or write data transfer occurs following the instruction byte. logic high indicates read operation. logic 0 indicates a write operation. bit 6, bit 5, and bit 4 are dummy bits (dont care). a3, a2, a1, a0bit 3, bit 2, bit 1, and bit 0 determine which register is accessed during the data transfer portion of the communication cycle (see table 8 for register address details). serial interface port pin descriptions sclk serial clock (pin 21). the serial clock pin is used to synchronize data to and from the ad9854 and to run the internal state machines. the sclk maximum frequency is 10 mhz. cs chip select (pin 22). active low input that allows more than one device on the same serial communication line. the sdo and sdio pins go to a high impedance state when this input is high. if this pin is driven high during a communication cycle, the cycle is suspended until cs is reactivated low. the chip select pin can be tied low in systems that maintain control of sclk. sdio serial data i/o (pin 19). data is always written to the ad9854 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by bit 0 of register address 20 hex. the default is logic 0, which configures the sdio pin as bidirectional. sdo serial data out (pin 18). data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9854 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. io reset synchronize i/o port (pin 17). synchronizes the i/o port state machines without affecting the contents of the addressable registers. an active high input on the io reset pin causes the current communication cycle to terminate. after the io reset pin returns low (logic 0), another communication cycle can begin, starting with the instruction byte. notes on serial port operation the ad9854 serial port configuration bits reside in bit 1 and bit 0 of register address 20 hex. it is important to note that the configuration changes immediately upon a valid i/o update. for multibyte transfers, writing to this register can occur during the middle of a communication cycle. the user must compensate for this new configuration for the remainder of the current com- munication cycle. the system must maintain synchronization with the ad9854; otherwise, the internal control logic is not able to recognize further instructions. for example, if the system sends the instruction to write a 2-byte register and then pulses the sclk pin for a 3-byte register (24 additional sclk rising edges), communication synchronization is lost. in this case, the first 16 sclk rising edges after the instruction cycle properly write the first two data bytes into the ad9854, but the subsequent eight rising sclk edges are interpreted as the next instruction byte, not the final byte of the previous communication cycle. in the case where synchronization is lost between the system and the ad9854, the io reset pin provides a means to re- establish synchronization without reinitializing the entire chip. asserting the io reset pin (active high) resets the ad9854 serial port state machine, terminating the current i/o operation and forcing the device into a state in which the next eight sclk rising edges are understood to be an instruction byte. the io reset pin must be deasserted (low) before the next instruction byte write can begin. any information written to the ad9854 registers during a valid communication cycle prior to loss of synchroni- zation remains intact. sclk sdio t pre t dsu t sclkpwh t sclkpwl t sclk t dhld second bit first bit symbol min definition cs setup time period of serial data clock serial data setup time serial data clock pulse width high serial data clock pulse width low serial data hold time t pre t sclk t dsu t sclkpwh t sclkpw l t dhld 30ns 100ns 30ns 40ns 40ns 0ns cs 00636-056 figure 56. timing diagram for data write to ad9854 instruction cycle data transfer instruction byte s dio data transfer data b yt e 1 data b yt e 2 data b yt e 3 sdo cs 00636-057 figure 57. timing diagram for read from ad9854
ad9854 rev. e | page 38 of 52 msb/lsb transfers the ad9854 serial port can support msb- and lsb-first data formats. this functionality is controlled by bit 1 of serial register bank 20 hex. when this bit is set active high, the ad9854 serial port is in lsb-first format. this bit defaults low, to the msb-first format. the instruction byte must be written in the format indicated by bit 1 of serial register bank 20 hex. therefore, if the ad9854 is in lsb-first mode, the instruction byte must be written from least significant bit to most significant bit. control register description the control register is located in the shaded portion of table 8 at address 1d to address 20 hex. it is composed of 32 bits. bit 31 is located at the top left position, and bit 0 is located in the lower right position of the shaded portion. in the text that follows, the register descriptions have been subdivided to make it easier to locate the text associated with specific control categories. cr [31:29] are open. cr [28] is the comparator power-down bit. when this bit is set (logic 1), its signal indicates to the comparator that a power- down mode is active. this bit is an output of the digital section and is an input to the analog section. cr [27] must always be written to logic 0. writing this bit to logic 1 causes the ad9854 to stop functioning until a master reset is applied. cr [26] is the q dac power-down bit. when this bit is set (logic 1), it indicates to the q dac that a power-down mode is active. cr [25] is the full dac power-down bit. when this bit is set (logic 1), it indicates to both the i and q dacs, as well as the reference, that a power-down mode is active. cr [24] is the digital power-down bit. when this bit is set (logic 1), its signal indicates to the digital section that a power- down mode is active. within the digital section, the clocks are forced to dc, effectively powering down the digital section. in this state, the pll still accepts the refclk signal and continues to output the higher frequency. cr [23] is reserved. write to 0. cr [22] is the pll range bit, which controls the vco gain. the power-up state of the pll range bit is logic 1; a higher gain is required for frequencies greater than 200 mhz. cr [21] is the bypass pll bit, active high. when this bit is active, the pll is powered down and the refclk input is used to drive the system clock signal. the power-up state of the bypass pll bit is logic 1 with pll bypassed. cr [20:16] bits are the pll multiplier factor. these bits are the refclk multiplication factor unless the bypass pll bit is set. the pll multiplier valid range is from 4 to 20, inclusive. cr [15] is the clear accumulator 1 bit. this bit has a one-shot type of function. when this bit is written active (logic 1), a clear accumulator 1 signal is sent to the dds logic, resetting the accumulator value to 0. the bit is then automatically reset, but the buffer memory is not reset. this bit allows the user to easily create a sawtooth frequency sweep pattern with minimal intervention. this bit is intended for chirp mode only, but its function is still retained in other modes. cr [14] is the clear accumulator bit. when this bit is active high, it holds both the accumulator 1 and accumulator 2 values at 0 for as long as the bit is active. this allows the dds phase to be initialized via the i/o port. cr [13] is the triangle bit. when this bit is set, the ad9854 automatically performs a continuous frequency sweep from f1 to f2 frequencies and back. this results in a triangular frequency sweep. when this bit is set, the operating mode must be set to ramped fsk. cr [12] is the source q dac bit. when this bit is set high, the q path dac accepts data from the q dac register. cr [11:9] are the three bits that describe the five operating modes of the ad9854: 0x0 = single-tone mode 0x1 = fsk mode 0x2 = ramped fsk mode 0x3 = chirp mode 0x4 = bpsk mode
ad9854 rev. e | page 39 of 52 sdio d 7 i 7 s clk instruction cycle d a t a transfer cycle i 6 i 5 i 4 i 3 i 0 i 2 i 1 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cs 00636-058 figure 58. serial port write timing clock stall low sdio d o7 d o6 d o5 d o4 d o3 d o2 d o1 d o0 s clk instruction cycle don't care sdo data transfer cycle i 7 i 6 i 5 i 4 i 3 i 0 i 2 i 1 cs 0 0636-059 figure 59. 3-wire serial port read timing clock stall low d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sdio sclk instruction cycle d a t a transfer cycle i 7 i 6 i 5 i 4 i 3 i 0 i 2 i 1 cs 00636-060 figure 60. serial port write timing clock stall high i 7 i 6 i 5 i 4 i 3 i 0 i 2 i 1 sdio s cl k instruction cycle d a t a transfer cycle d o7 d o6 d o5 d o4 d o3 d o2 d o1 d o0 cs 00636-061 figure 61. 2-wire serial port read timing clock stall high cr [8] is the internal update active bit. when this bit is set to logic 1, the i/o ud clk pin is an output and the ad9854 generates the i/o ud clk signal. when this bit is set to logic 0, external i/o ud clk functionality is performed and the i/o ud clk pin is configured as an input. cr [7] is reserved. write to 0. cr [6] is the inverse sinc filter bypass bit. when this bit is set, the data from the dds block goes directly to the output shaped keying logic, and the clock to the inverse sinc filter is stopped. default is clear with the filter enabled. cr [5] is the shaped keying enable bit. when this bit is set, the output ramping function is enabled and is performed in accordance with the cr [4] bit requirements. cr [4] is the internal/external output shaped keying control bit. when this bit is set to logic 1, the output shaped keying factor is internally generated and applied to both the i and q paths. when this bit is cleared (default), the output shaped keying function is externally controlled by the user, and the ouput shaped keying factor is the value of the i and q output shaped keying factor register. the two registers that are the output shaped keying factors also default low such that the output is off at power-up until the device is programmed by the user. cr [3:2] are reserved. write to 0. cr [1] is the serial port msb-/lsb-first bit. default is low, msb first. cr [0] is the serial port sdo active bit. default is low, inactive.
ad9854 rev. e | page 40 of 52 power dissipation and thermal considerations the ad9854 is a multifunctional, high speed device that targets a wide variety of synthesizer and agile clock applications. the numerous innovative features contained in the device each consume incremental power. if enabled in combination, the safe thermal operating conditions of the device may be exceeded. careful analysis and consideration of power dissipation and thermal management is a critical element in the successful application of the ad9854. however, in most cases, disabling the inverse sinc filter prevents exceeding the maximum die temperature, because the inverse sinc filter consumes approximately 30% of the total power. the ad9854 is specified to operate within the industrial tem- perature range of ?40c to +85c. this specification is conditional, however, such that the absolute maximum junction temperature of 150c is not exceeded. at high operating temperatures, extreme care must be taken when operating the device to avoid exceeding the junction temperature and potentially damaging the device. many variables contribute to the operating junction temperature within the device, including ? package style ? selected mode of operation ? internal system clock speed ? supply voltage ? ambient temperature the combination of these variables determines the junction temperature within the ad9854 for a given set of operating conditions. the ad9854 is available in two package styles: a thermally enhanced surface-mount package with an exposed heat sink and a standard (nonthermally enhanced) surface-mount package. the thermal impedance of these packages is 16.2c/w and 38c/w, respectively, measured under still air conditions. thermal impedance the thermal impedance of a package can be thought of as a thermal resistor that exists between the semiconductor surface and the ambient air. the thermal impedance is determined by the package material and the physical dimensions of the package. the dissipation of the heat from the package is directly dependent on the ambient air conditions and the physical connection made between the ic package and the pcb. adequate dissipation of heat from the ad9854 relies on all power and ground pins of the device being soldered directly to a copper plane on a pcb. in addition, the thermally enhanced package of the ad9854asvz has an exposed paddle on the bottom of the package that must be soldered to a large copper plane, which, for convenience, can be the ground plane. sockets for either package style of the device are not recommended. junction temperature considerations the power dissipation (p diss ) of the ad9854 in a given application is determined by many operating conditions. some of the conditions have a direct relationship with p diss , such as supply voltage and clock speed, but others are less deterministic. the total power dissipation within the device and its effect on the junction temperature must be considered when using the device. the junction temperature of the device is given by ( thermal impedance power consumption ) + ambient temperature the maximum ambient temperature combined with the maximum junction temperature establishes the following power consumption limits for each package: 4.06 w for asvz models and 1.71 w for astz models. supply voltage the supply voltage affects power dissipation and junction temperature because p diss = v i . users should design for 3.3 v nominal; however, the device is guaranteed to meet specifications over the full temperature range and over the supply voltage range of 3.135 v to 3.465 v. clock speed clock speed directly and linearly influences the total power dissipation of the device and therefore the junction temperature. as a rule, to minimize power dissipation, the user should select the lowest possible internal clock speed to support a given application. typically, the usable frequency output bandwidth from a dds is limited to 40% of the clock rate to ensure that the requirements of the output low-pass filter are reasonable. for a typical dds application, the system clock frequency should be 2.5 times the highest desired output frequency. mode of operation the selected mode of operation of the ad9854 significantly influences the total power consumption. although the ad9854 offers many features targeting a wide variety of applications, the device is designed to operate with only a few features enabled at once for a given application. if multiple features are enabled at higher clock speeds, the maximum junction temperature of the die may be exceeded, severely limiting the long-term reliability of the device. figure 62 and figure 63 show the power requirements associated with each feature of the ad9854. these graphs should be used as a guide in determining power consumption for specific feature sets. figure 62 shows the supply current consumed by the ad9854 over a range of frequencies for two possible configurations. all circuits enabled means that the output scaling multipliers, the inverse sinc filter, the q dac, and the on-board comparator are enabled. basic configuration means that the output scaling
ad9854 rev. e | page 41 of 52 multipliers, the inverse sinc filter, the q dac, and the on-board comparator are disabled. frequency (mhz) 1400 20 supply curren t (ma) 1200 1000 800 600 400 200 0 60 100 140 180 220 260 300 all circuits enabled basic configuration 00636-062 notes this graph assumes that the ad9854 device is soldered to a multilayer pcb per the recommended best manufacturing practices and procedures for the given package type. figure 62. current consum ption vs. clock frequency figure 63 shows the approximate current consumed by each of four functions. frequency (mhz) 20 60 100 140 180 220 260 300 450 supply current (ma) 400 350 300 250 200 150 0 100 50 q dac 500 inverse sinc filter output scaling multipliers comparator 00636-063 notes t his graph assumes that the ad9854 device is s oldered to a multilayer pcb per the recommended best manufacturing practices and procedures for t he given package type. figure 63. current consumption by function vs. clock frequency evaluation of operating conditions the first step in applying the ad9854 is to select the internal clock frequency. clock frequency selections greater than 200 mhz require the use of the thermally enhanced package (ad9854asvz); other clock frequencies may allow the use of the standard plastic surface-mount package, but more information is needed to make that determination. the second evaluation step is to determine the maximum required operating temperature for the ad9854 in a given application. subtract this value from 150c, which is the maximum junction temperature allowed for the ad9854. for the extended industrial temperature range, the maximum operating temperature is 85c, which results in a difference of 65c. this is the maximum temperature gradient that the device can experience due to power dissipation. the third evaluation step is to divide the maximum temper- ature gradient by the thermal impedance to determine the maximum power dissipation allowed for the application. for example, 65c divided by the thermal impedance of the package being used yields the total power dissipation limit (4.06 w for the asvz models and 1.71 w for the astz models). therefore, for a 3.3 v nominal power supply voltage, the current consumed by the device with full operating conditions must not exceed 515 ma for the standard plastic package and 1242 ma for the thermally enhanced package. the total set of enabled functions and operating conditions of the ad9854 application must support these current consumption limits. to determine the suitability of a given ad9854 application in terms of the power dissipation requirements use figure 62 and figure 63 . these graphs assume that the ad9854 device is soldered to a multilayer pcb per the recommended best manufacturing practices and procedures for the given package type. this ensures that the specified thermal impedance specifications are achieved. thermally enhanced package mounting guidelines refer to the an-772 application note for details on mounting devices with an exposed paddle.
ad9854 rev. e | page 42 of 52 evaluation board an evaluation board package is available for the ad9854 dds device. this package consists of a pcb, software, and documentation to facilitate bench analysis of the devices performance. to ensure optimum dynamic performance from the device, users should familiarize themselves with the operation and performance capabilities of the ad9854 with the evaluation board and use the evaluation board as a pcb reference design. evaluation board instructions the ad9852/ad9854 revision e evaluation board includes either an ad9852asvz or ad9854asvz ic. the asvz package permits 300 mhz operation by virtue of its thermally enhanced design. this package has a bottom-side heat slug that must be soldered to the ground plane of the pcb directly beneath the ic. in this manner, the evaluation board pcb ground plane layer extracts heat from the ad9852 or ad9854 ic package. if device operation is limited to 200 mhz or less, the astz package can be used without a heat slug in customer installations over the full temperature range. evaluation boards for both the ad9852 and ad9854 are identical except for the installed ic. to assist in proper placement of the pin header shorting jumpers, the instructions refer to direction (left, right, top, bottom) as well as header pins to be shorted. pin 1 for each 3-pin header is marked on the pcb corresponding with the schematic diagram. when following these instructions, position the pcb so that the pcb text can be read from left to right. the board is shipped with the pin headers configuring the board as follows: ? refclk for the ad9852 or ad9854 is configured as differential. the differential clock signals are provided by the mc100lvel16d differential receiver. ? the input clock for the mc100lvel16d is single ended via j25. this signal may be 3.3 v cmos or a 2 v p-p sine wave capable of driving 50 (r13). ? both dac outputs from the ad9852 or ad9854 are routed through the two 120 mhz elliptical lp filters, and their outputs are connected to j7 (q, or control dac) and j6 (i, or cosine dac). ? the board is set up for software control via the printer port connector. ? the output currents of the dac are configured for 10 ma. general operating instructions load the cd software onto your pcs hard disk. the current software (version 1.72) supports windows? 95, windows 98, windows 2000, windows nt?, and windows xp. connect a printer cable from the pc to the ad9854 evaluation board printer port connector labeled j11. hardware preparation use the schematics (see figure 64 and figure 65 ) in conjunction with these instructions to become acquainted with the electrical functioning of the evaluation board. attach power wires to the co nnector labeled tb1 using the screw-down terminals. this connector is plastic and press-fits over a 4-pin header soldered to the board. table 11 lists the connections to each pin. table 11. power requirements for dut pins 1 avdd 3.3 v dvdd 3.3 v vcc 3.3 v ground for all dut analog pins for all dut digital pins for all other devices for all devices 1 dut = device under test. clock input, j25 attach refclk to the clock input, j25. this is a single-ended input that is routed to the mc100lvel16d for conversion to differential pecl output. this is accomplished by attaching a 2 v p-p clock or sine wave source to j25. note that this is a 50 impedance point set by r13. the input signal is ac-coupled and then biased to the center-switching threshold of the mc100lvel16d. to engage the differential clocking mode of the ad9854, pin 2 and pin 3 (the bottom two pins) of w3 must be connected with a shorting jumper. the signal arriving at the ad9854 is called the reference clock. when engaging the on-chip pll clock multiplier, this signal is the reference clock for the pll and the multiplied pll output becomes the system clock. if the pll clock multiplier is to be bypassed, the reference clock supplied by the user directly operates the ad9854 and is therefore the system clock. three-state control the w9, w11, w12, w13, w14, and w15 switch headers must be shorted to allow the provided software to control the ad9854 evaluation board via the printer port connector, j11. programming if programming of the ad9854 is not to be provided by the users pc and analog devices software, the w9, w11, w12, w13, w14, and w15 headers should be opened (shorting jumpers removed). this effectively detaches the pc interface and allows j10 (the 40-pin header) and j1 to assume control without bus contention. input signals on j10 and j1 going to the ad9854 should be 3.3 v cmos logic levels. low-pass filter testing the purpose of the 2-pin w7 and w10 headers (associated with j4 and j5) is to allow the two 50 , 120 mhz filters to be tested during pcb assembly without interference from other circuitry attached to the filter inputs. typically, a shorting jumper is
ad9854 rev. e | page 43 of 52 attached to each header to allow the dac signals to be routed to the filters. if the user wishes to test the filters, the shorting jumpers at w7 and w10 should be removed and 50 test signals should be applied at the j4 and j5 inputs to the 50 elliptic filters. users should refer to the schematic provided and to the following sections to properly position the remaining shorting jumpers. observing the unfiltered iout1 and the unfiltered iout2 dac signals the unfiltered dac outputs can be observed at j5 (the i, or cosine dac, signal) and j4 (the q, or control dac, signal). use the following procedure to route the two 50 terminated analog dac outputs to the smb connectors and to disconnect any other circuitry: 1. install shorting jumpers at w7 and w10. 2. remove the shorting jumper at w16. 3. remove the shorting jumper from the 3-pin w1 header. 4. install a shorting jumper on pin 1 and pin 2 (bottom two pins) of the 3-pin w4 header. the raw dac outputs may appear as a series of quantized (stepped) output levels that may not resemble a sine wave until they are filtered. the default 10 ma output current develops a 0.5 v p-p signal across the on-board 50 termination. if the observation equipment offers 50 inputs, the dac develops only 0.25 v p-p due to the double termination. if using the ad9852 evaluation board, the user can control iout2 (the control dac output) by using the serial or parallel ports. the 12-bit, twos complement value(s) is/are written to the control dac register that sets the iout2 output to a static dc level. allowable hexadecimal values are 7ff (maximum) to 800 (minimum), with all 0s being midscale. rapidly changing the contents of the control dac register (up to 100 msps) allows iout2 to assume any waveform that can be programmed. observing the filtered iout 1 and the filtered iout2 the filtered i (cosine dac) and q (control dac) outputs can be observed at j6 (for the i signal) and j7 (for the q signal). use the following procedure to route the 50 (input and output z) low-pass filters into the pathways of the i and q signals to remove images, aliased harmonics, and other spurious signals that are greater than approximately 120 mhz: 1. install shorting jumpers at w7 and w10. 2. install a shorting jumper at w16. 3. install a shorting jumper on pin 1 and pin 2 (bottom two pins) of the 3-pin w1 header. 4. install a shorting jumper on pin 1 and pin 2 (bottom two pins) of the 3-pin w4 header. 5. install a shorting jumper on pin 2 and pin 3 (bottom two pins) of the 3-pin w2 and w8 headers. the resulting i and q signals appear as nearly pure sine waves and 90 out of phase with each other. these filters are designed with the assumption that the system clock speed is at or near its maximum speed (300 mhz). if the system clock speed is much less than 300 mhz, for example 200 mhz, it is possible, or inevitable, that unwanted dac products other than the fundamental signal will be passed by the low-pass filters. if the ad9852 evaluation board is used, any reference to the q signal should be interpreted as meaning the control dac. observing the filtered iout1 and the filtered iout1 the filtered i dac outputs can be observed at j6 (the true signal) and j7 (the complementary signal). use the following procedure to route the 120 mhz low-pass filters in the true and complementary output paths of the i dac to remove images, aliased harmonics, and other spurious signals that are greater than approximately 120 mhz: 1. install shorting jumpers at w7 and w10. 2. install a shorting jumper at w16. 3. install a shorting jumper on pin 2 and pin 3 (top two pins) of the 3-pin w1 header. 4. install a shorting jumper on pin 2 and pin 3 (top two pins) of the 3-pin w4 header. 5. install a shorting jumper on pin 2 and pin 3 (bottom two pins) of the 3-pin w2 and w8 headers. the resulting signals appear as nearly pure sine waves and 180 out of phase with each other. if the system clock speed is much less than 300 mhz, for example 200 mhz, it is possible, or inevitable, that unwanted dac products other than the fundamental signal will be passed by the low-pass filters. connecting the high speed comparator to connect the high speed comparator to the dac output signals use either the quadrature filtered output configuration (for ad9854 only) or the complementary filtered output configuration outlined in the previous section (for both the ad9854 and the ad9852). follow step 1 through step 4 in either the observing the filtered iout1 and the filtered iout2 section or the observing the filtered iout1 and the filtered iout1 section. then install a shorting jumper on pin 1 and pin 2 (top two pins) of the 3-pin w2 and w8 headers. this reroutes the filtered signals away from the output connectors (j6 and j7) and to the 100 configured comparator inputs. this sets up the comparator for differential input without affecting the comparator output duty cycle, which should be approximately 50% in this configuration. the user can change the value of r set resistor r2 from 3.9 k to 1.95 k to receive more robust signals at the comparator inputs. this decreases jitter and extends the operating range of the comparator. to implement this change install a shorting jumper at w6, which provides a second 3.9 k chip resistor (r20) in parallel with that prov ided by r2. this boosts the dac
ad9854 rev. e | page 44 of 52 output current from 10 ma to 20 ma and doubles the peak-to- peak output voltage developed across the loads, thus resulting in more robust signals at the comparator inputs. single-ended configuration to connect the high speed comparator in a single-ended configuration so that the duty cycle or pulse width can be controlled, a dc threshold voltage must be present at one of the comparator inputs. the user can supply this voltage using the control dac. a 12-bit, twos complement value is written to the control dac register that sets the iout2 output to a static dc level. allowable hexadecimal values are 7ff (maximum) to 800 (minimum), with all 0s being midscale. the iout1 channel continues to output a filtered sine wave programmed by the user. these two signals are routed to the comparator by using the 3-pin w2 and w8 header switches. use of the configuration described in the observing the filtered iout1 and the filtered iout2 section is required. follow step 1 through step 4 in this section, and then install a shorting jumper on pin 1 and pin 2 (top two pins) of the 3-pin w2 and w8 headers. the user can change the value of r set resistor r2 from 3.9 k to 1.95 k to receive more robust signals at the comparator inputs. this decreases jitter and extends the operating range of the comparator. to implement this change install a shorting jumper at w6, which provides a second 3.9 k chip resistor (r20) in parallel with that provided by r2. using the provided software the evaluation software is provided on a cd, along with a brief set of instructions. use the instructions in conjunction with the ad9852 or ad9854 data sheet and the ad9852 or ad9854 evaluation board schematic. the cd contains the following: ? the ad9852/ad9854 evaluation software ? ad9854 evaluation board instructions ? ad9854 data sheet ? ad9854 evaluation board schematics ? ad9854 pcb layout several numerical entries, such as frequency and phase infor- mation, require pressing enter to register the information. for example, if a new frequency is input but does not take effect when load is clicked, the user probably neglected to press enter after typing the new frequency information. normal operation of the ad9852/ad9854 evaluation board begins with a master reset. after this reset, many of the default register values are depicted in the software control panel. the reset command sets the dds output amplitude to minimum and 0 hz, zero phase offset, as well as other states that are listed in the register layout table ( tabl e 8 for ad9854). the next programming block should be the reference clock and multiplier because this information is used to determine the proper 48-bit frequency tuning words that are entered and later calculated. the output amplitude defaults to the 12-bit, straight binary multiplier values of the i (cosine dac) multiplier register of 000 hex; no output (dc) should be seen from the dac. set the multiplier amplitude in the output amplitude dialog box to a substantial value, such as fff hex. the digital multiplier can be bypassed by selecting output amplitude is always full scale, but this usually does not result in the best spurious-free dynamic range (sfdr). the best sfdr, achieving improvements of up to 11 db, is obtained by routing the signal through the digital multiplier and then reducing the multiplier amplitude. for instance, fc0 hex produces less spurious signal amplitude than fff hex. if sfdr must be maximized, this exploitable and repeatable phenomenon should be investigated in the given application. this phenomenon is more readily observed at higher output frequencies, where good sfdr becomes more difficult to achieve. refer to this data sheet and the evaluation board schematic to understand the available functions of the ad9854 and how the software responds to programming commands. support applications assistance is available for the ad9854, the ad9854 pcb evaluation board, and all other analog devices products. call 1-800-analogd or visit www.analog.com/dds .
ad9854 rev. e | page 45 of 52 table 12. ad9854 customer evaluation board (ad9854 pcb > u1 = ad9854asvz) item qty reference designator device package value min tol manufacturer manufacturer part no. 1 3 c1, c2, c45 capacitor 0805 805 0.01 f, 50 v, x7r 10% kemet corp. c0805c103k5ractu 2 21 c7, c8, c9, c10, c11, c12, c13, c14, c16, c17, c18, c19, c20, c22, c23, c24, c26, c27, c28, c29, c44 capacitor 0603 603 0.1 f, 50 v, x7r 10% murata manufacturing co., ltd. grm188r71h104ka93d 3 2 c4, c37 capacitor 1206 1206 27 pf, 50 v, npo 5% yageo corporation cc1206jrnpo9bn270 4 2 c5, c38 capacitor 1206 1206 47 pf, 50 v, npo 5% yageo corporation cc1206jrnpo9bn470 5 3 c6, c21, c25 capacitor tajc tajc 10 f, 16 v, taj 10% avx tajc106k016r 6 2 c30, c39 capacitor 1206 1206 39 pf, 50 v, npo 5% yageo corporation cc1206jrnpo9bn390 7 2 c31, c40 capacitor 1206 1206 22 pf, 50 v, npo 5% yageo corporation cc1206jrnpo9bn220 8 2 c32, c41 capacitor 1206 1206 2.2 pf, 50 v, npo 0.25 pf yageo corporation cc1206crnpo9bn2r2 9 2 c33, c42 capacitor 1206 1206 12 pf, 50 v, npo 5% yageo corporation 1206cg120j9b200 10 2 c34, c43 capacitor 1206 1206 8.2 pf, 50 v, npo 0.5 pf yageo corporation cc1206drnpo9bn8r2 11 9 j1, j2, j3, j4, j5, j6, j7, j25, j26 smb str-pc mnt n/a n/a emerson/johnson 131-3701-261 12 1 j10 40-pin header header 40 n/a n/a samtec, inc. tsw-120-23-l-d 13 4 l1, l2, l3, l5 inductor coil 1008cs 68 nh 2% coilcraft, inc. 1008cs-680xglb 14 2 l4, l6 inductor coil 1008cs 82 nh 2% coilcraft, inc. 1008cs-820xglb 15 2 r1, r5 res_sm 1206 49.9 , ? w 1% panasonic-ecg erj-8enf49r9v 16 2 r2, r20 res_sm 1206 3.92 k, ? w 1% panasonic-ecg erj-8enf3921v 17 2 r3, r7 res_sm 1206 24.9 , ? w 1% panasonic-ecg erj-8enf24r9 18 1 r4 res_sm 1206 1.3 k, ? w 1% panasonic-ecg erj-8enf1301v 19 4 r6, r11, r12, r13 res_sm 1206 49.9 , ? w 1% panasonic-ecg erj-8enf49r9v 20 1 r8 res_sm 1206 2 k, ? w 1% panasonic-ecg erj-8enf2001v 21 2 r9, r10 res_sm 1206 100 , ? w 1% panasonic-ecg erj-8enf1000v 22 4 r15, r16, r17, r18 res_sm 1206 10 k, ? w 1% panasonic-ecg erj-8enf1002v 23 1 rp1 resistor network sip-10p 10 k 2% bourns 4610x-101-103lf 24 1 tb1 tb4 4-position terminal n/a n/a wieland electric, inc. plug: 25.602.2453.0; terminal strip: z5.530.3425.0 25 1 u1 ad9854 sv-80 n/a n/a analog devices, inc. ad9854asvz 26 1 u2 74hc125d 14 soic n/a n/a texas instruments incorporated sn74hc125dr
ad9854 rev. e | page 46 of 52 item qty reference designator device package value manufacturer manufacturer part no. min tol 27 1 u3 primary 8 soic n/a n/a on semiconductor primary: mc10ep16dgos secondary 8 soic n/a n/a on semiconductor secondary: mc100lvel16dgos 28 4 u4, u5, u6, u7 74hc14 14 soic n/a n/a texas instruments incorporated sn74hc14dr 29 3 u8, u9, u10 74hc574 20 soic n/a n/a texas instruments incorporated sn74hc574dwr 30 1 j11 c36crpx 36crp n/a n/a tyco electronics corporation 5552742-1 31 6 w1, w2, w3, w4, w8, w17 3-pin header sip-3p n/a n/a samtec, inc. tsw-103-07-s-s 32 10 w6, w7, w9, w10, w11, w12, w13, w14, w15, w16 2-pin header sip-2p n/a n/a samtec, inc. tsw-102-07-s-s 33 6 w1, w2, w3, w4, w8, w17 jumpers n/a black n/a samtec, inc. snt-100-bk-g 34 10 w6, w7, w9, w10, w11, w12, w13, w14, w15, w16 jumpers n/a black n/a samtec, inc. snt-100-bk-g 35 2 n/a self-tapping screw 4C40, phillips pan head n/a n/a 90410a107 36 4 n/a adhesive feet n/a black n/a 3m sj-5518 37 1 ad9852/54 pcb n/a n/a n/a n/a gs02669 rev. e 38 2 r14, r19 res_sm 1206 0 , ? w 5% panasonic-ecg erj-8gey0r00v 39 4 n/a pin socket (open end) tyco electronics corporation 5-5330808-6 40 1 y1 xtal cosc n/a n/a optional optional
ad9854 rev. e | page 47 of 52 d7 d6 d5 d4 d3 d2 d1 d0 dvdd1 dvdd2 dgnd1 dgnd2 nc addr5 addr4 addr3 addr2 addr1 addr0 updclk u1 ad9854 top view (not to scale) pllvdd pllgnd nc4 nc3 rset dacbypass avdd2 agnd2 iout2 iout2 avdd iout1 iout1 agnd gnd2 compvdd vinn vinp gnd compgnd pllflt gnd3 nc5 diffclken clkvdd clkgnd gnd4 refclk refclk spselect mreset optgnd dvdd6 dvdd7 dgnd6 dgnd7 dgnd8 dgnd9 dvdd8 dvdd9 coutgnd2 coutgnd coutvdd2 coutvdd vout nc2 dacdgnd2 dacdgnd dacdvdd2 dacdvdd osk fsk/bpsk/hold dgnd5 dgnd4 dvdd5 dvdd4 dvdd3 rd dgnd3 wr j6 j8 j16 j17 j18 j19 j20 j21 j22 j24 j23 j14 j13 j12 j11 gnd j15 w6 r2 3.92k ? r20 3.92k ? avdd c45 0.01f r1 49.9 ? j4 w7 w1 1 gnd gnd avdd r3 24.9 ? w10 w16 d7 d6 d5 d4 d3 d2 d1 d0 dvdd dvdd gnd gnd a5 a4 a3 a2/io reset a1/sdo a0/sdio i/o ud clk avdd avdd avdd rd/cs dvdd dvdd dvdd osk avdd avdd avdd avdd avdd dvdd avdd gnd dvdd w3 r4 1.3k ? c1 0.01f clk8 clk pmode reset gnd gnd dvdd gnd r13 49.9 ? c2 0.01f out gnd nc 3.3v mc100lvel16dgos l5 68nh vee vbb vcc u3 y1 d d q q dvdd 14 7 8 1 2 3 7 6 c25 10f c21 10f c24 0.1f c23 0.1f c22 0.1f c27 0.1f c8 0.1f c44 0.1f gnd dvdd j10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 adr5 adr4 adr3 adr2 adr1 adr0 udclk wr rd pmode osk reset d7 d6 d5 d4 d3 d2 d0 d1 120mhz low-pass filter 120mhz low-pass filter w4 r5 49.9 ? w17 r8 2k ? 1 dvdd r11 49.9 ? r12 49.9 ? r19 0 ? r14 0 ? clkb clk j3 gnd c37 27pf c38 47pf c39 39pf c40 22pf w8 1 l1 68nh l6 82nh c41 2.2pf c42 12pf c43 8.2pf c31 22pf c30 39pf c5 47pf c4 27pf l4 82nh l2 68nh c32 2.2pf c33 12pf c34 8.2pf gnd j6 w2 1 gnd 1 r7 24.9 ? r6 49.9 ? fdata 54 8 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd nc = no connect l3 68nh r9 100 ? gnd r10 100 ? gnd 1 gnd gnd gnd gnd gnd gnd tb1 dvdd avdd vcc 1 2 3 4 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 gnd gnd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 j26 gnd j1 gnd j5 gnd gnd j7 gnd j25 c6 10f c7 0.1f c29 0.1f c9 0.1f c10 0.1f c11 0.1f c13 0.1f gnd avdd c20 0.1f c19 0.1f c18 0.1f c14 0.1f c26 0.1f c28 0.1f gnd vcc c12 0.1f c17 0.1f c16 0.1f j2 gnd wr/sclk 00636-068 figure 64. evaluation board schematic
ad9854 rev. e | page 48 of 52 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 8d 1d gnd: 10 11 1 en 74hc574 c1 vcc: 20 d0 d1 d2 d3 d4 d5 d6 d7 u8 1 3 5 9 11 13 7 74hc14 14 vcc gnd 2 4 6 8 10 12 1a 2a 3a 4a 5a 6a 1y 2y 3y 4y 5y 6y gnd vcc u5 4 6 8 3 5 9 2 7 1 j11 36pinconn gnd:[19:30] 11 13 10 12 14 a0 c0 a1 a2 a3 a4 a5 a6 a7 b6 b7 b5 b4 c1 c2 b3 c3 u6 u7 vcc r15 10k ? r16 10k ? r17 10k ? vcc vcc gnd: 10 11 1 en 74hc574 c1 vcc: 20 addr5 addr4 addr3 addr2 u9 vcc gnd: 10 11 1 en c1 74hc574 vcc: 20 reset udclk pmode oramp fdata u4 74hc125d gnd 1g 1a 1y 2g 2a 2y vcc 4g 4a 4y 3g 3a 3y u2 gnd 1 2 3 4 5 6 7 13 12 11 10 9 8 14 vcc vcc u10 w11 addr1 addr0 w14 w12 w13 w9 vcc r18 10k ? gnd w15 vcc rp1 10k ? 13 5 9 2 4 6 810 7 1 3 5 9 11 13 7 74hc14 14 vcc gnd 2 4 6 8 10 12 1a 2a 3a 4a 5a 6a 1y 2y 3y 4y 5y 6y gnd vcc 1 3 5 9 11 13 7 74hc14 14 vcc gnd 2 4 6 8 10 12 1a 2a 3a 4a 5a 6a 1y 2y 3y 4y 5y 6y gnd vcc 1 3 5 9 11 13 7 74hc14 14 vcc gnd 2 4 6 8 10 12 1a 2a 3a 4a 5a 6a 1y 2y 3y 4y 5y 6y gnd vcc 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 8d 1d 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 8d 1d 31 32 36 vcc vcc vcc wr rd 00636-069 figure 65. evaluation board schematic
ad9854 rev. e | page 49 of 52 00636-070 figure 66. assembly drawing 00636-071 figure 67. top routing layer, layer 1
ad9854 rev. e | page 50 of 52 00636-072 figure 68. power plane layer, layer 3 00636-073 figure 69. ground plane layer, layer 2
ad9854 rev. e | page 51 of 52 00636-074 figure 70. bottom routing layer, layer 4
ad9854 rev. e | page 52 of 52 outline dimensions compliant to jedec standards ms-026-aec-hd 091506-a 0.75 0.60 0.45 1.20 max 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 0.27 0.22 0.17 0.65 bsc lead pitch bottom view (pins up) 9.50 sq exposed pad 20 21 21 40 40 41 61 61 60 41 60 80 80 1 20 1 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 figure 71. 80-lead thin quad flat package, exposed pad [tqfp_ep] (sv-80-4) dimensions shown in millimeters compliant to jedec standards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 top view (pins down) pin 1 051706-a figure 72. 80-lead low profile quad flat package [lqfp] (st-80-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad9854asvz 1 ?40c to +85c 80-lead thin quad flat package, exposed pad [tqfp_ep] sv-80-4 AD9854AST ?40c to +85c 80-lead low prof ile quad flat package [lqfp] st-80-2 AD9854ASTz 1 ?40c to +85c 80-lead low profile quad flat package [lqfp] st-80-2 ad9854/pcb evaluation board 1 z = rohs compliant part. ?2002C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c00636-0-7/07(e)

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